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Commit 26f9ec9a authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source() 



Both functions have the same code to disable PSR, so let's reuse that
code instead of duplicate.

Suggested-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181106190843.18009-1-jose.souza@intel.com
parent 53cc6880

drivers/gpu/drm/i915/intel_psr.c

+21 −29
Original line number Diff line number Diff line
@@ -657,6 +657,25 @@ void intel_psr_enable(struct intel_dp *intel_dp, 
	mutex_unlock(&dev_priv->psr.lock);

}



static void intel_psr_exit(struct drm_i915_private *dev_priv)

{

	u32 val;



	if (!dev_priv->psr.active)

		return;



	if (dev_priv->psr.psr2_enabled) {

		val = I915_READ(EDP_PSR2_CTL);

		WARN_ON(!(val & EDP_PSR2_ENABLE));

		I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);

	} else {

		val = I915_READ(EDP_PSR_CTL);

		WARN_ON(!(val & EDP_PSR_ENABLE));

		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);

	}

	dev_priv->psr.active = false;

}



static void

intel_psr_disable_source(struct intel_dp *intel_dp)

{
@@ -666,20 +685,14 @@ intel_psr_disable_source(struct intel_dp *intel_dp) 
		i915_reg_t psr_status;

		u32 psr_status_mask;



		intel_psr_exit(dev_priv);



		if (dev_priv->psr.psr2_enabled) {

			psr_status = EDP_PSR2_STATUS;

			psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;



			I915_WRITE(EDP_PSR2_CTL,

				   I915_READ(EDP_PSR2_CTL) &

				   ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));



		} else {

			psr_status = EDP_PSR_STATUS;

			psr_status_mask = EDP_PSR_STATUS_STATE_MASK;



			I915_WRITE(EDP_PSR_CTL,

				   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);

		}



		/* Wait till PSR is idle */
@@ -687,8 +700,6 @@ intel_psr_disable_source(struct intel_dp *intel_dp) 
					    psr_status, psr_status_mask, 0,

					    2000))

			DRM_ERROR("Timed out waiting for PSR Idle State\n");



		dev_priv->psr.active = false;

	} else {

		if (dev_priv->psr.psr2_enabled)

			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
@@ -926,25 +937,6 @@ static void intel_psr_work(struct work_struct *work) 
	mutex_unlock(&dev_priv->psr.lock);

}



static void intel_psr_exit(struct drm_i915_private *dev_priv)

{

	u32 val;



	if (!dev_priv->psr.active)

		return;



	if (dev_priv->psr.psr2_enabled) {

		val = I915_READ(EDP_PSR2_CTL);

		WARN_ON(!(val & EDP_PSR2_ENABLE));

		I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);

	} else {

		val = I915_READ(EDP_PSR_CTL);

		WARN_ON(!(val & EDP_PSR_ENABLE));

		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);

	}

	dev_priv->psr.active = false;

}



/**

 * intel_psr_invalidate - Invalidade PSR

 * @dev_priv: i915 device