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Commit 26f8590c authored by Thierry Reding's avatar Thierry Reding Committed by Stephen Boyd
Browse files

clk: tegra: Make vic03 a child of pll_c3 



By default, the vic03 clock is a child of pll_m but that runs at 924 MHz
which is too fast for VIC. Make vic03 a child of pll_c3 by default so it
will run at a supported frequency.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent ce397d21

drivers/clk/tegra/clk-tegra124.c

+1 −0
Original line number Diff line number Diff line
@@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { 
	{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },

	{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },

	{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },

	{ TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },

	/* must be the last entry */

	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },

};