Loading drivers/clk/qcom/clk-rpmh.c +3 −0 Original line number Diff line number Diff line Loading @@ -446,6 +446,7 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = { }; DEFINE_CLK_RPMH_ARC(lahaina, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_VRM_OPT(lahaina, div_clk1, div_clk1_ao, "divclka1", 2); DEFINE_CLK_RPMH_VRM(lahaina, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(lahaina, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(lahaina, rf_clk1, rf_clk1_ao, "rfclka1", 1); Loading @@ -460,6 +461,8 @@ DEFINE_CLK_RPMH_BCM(lahaina, hwkm, "HK0"); static struct clk_hw *lahaina_rpmh_clocks[] = { [RPMH_CXO_CLK] = &lahaina_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &lahaina_bi_tcxo_ao.hw, [RPMH_DIV_CLK1] = &lahaina_div_clk1.hw, [RPMH_DIV_CLK1_A] = &lahaina_div_clk1_ao.hw, [RPMH_LN_BB_CLK1] = &lahaina_ln_bb_clk1.hw, [RPMH_LN_BB_CLK1_A] = &lahaina_ln_bb_clk1_ao.hw, [RPMH_LN_BB_CLK2] = &lahaina_ln_bb_clk2.hw, Loading include/dt-bindings/clock/qcom,rpmh.h +2 −0 Original line number Diff line number Diff line Loading @@ -32,5 +32,7 @@ #define RPMH_PKA_CLK 23 #define RPMH_HWKM_CLK 24 #define RPMH_QPIC_CLK 25 #define RPMH_DIV_CLK1 26 #define RPMH_DIV_CLK1_A 27 #endif Loading
drivers/clk/qcom/clk-rpmh.c +3 −0 Original line number Diff line number Diff line Loading @@ -446,6 +446,7 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = { }; DEFINE_CLK_RPMH_ARC(lahaina, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); DEFINE_CLK_RPMH_VRM_OPT(lahaina, div_clk1, div_clk1_ao, "divclka1", 2); DEFINE_CLK_RPMH_VRM(lahaina, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); DEFINE_CLK_RPMH_VRM(lahaina, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); DEFINE_CLK_RPMH_VRM(lahaina, rf_clk1, rf_clk1_ao, "rfclka1", 1); Loading @@ -460,6 +461,8 @@ DEFINE_CLK_RPMH_BCM(lahaina, hwkm, "HK0"); static struct clk_hw *lahaina_rpmh_clocks[] = { [RPMH_CXO_CLK] = &lahaina_bi_tcxo.hw, [RPMH_CXO_CLK_A] = &lahaina_bi_tcxo_ao.hw, [RPMH_DIV_CLK1] = &lahaina_div_clk1.hw, [RPMH_DIV_CLK1_A] = &lahaina_div_clk1_ao.hw, [RPMH_LN_BB_CLK1] = &lahaina_ln_bb_clk1.hw, [RPMH_LN_BB_CLK1_A] = &lahaina_ln_bb_clk1_ao.hw, [RPMH_LN_BB_CLK2] = &lahaina_ln_bb_clk2.hw, Loading
include/dt-bindings/clock/qcom,rpmh.h +2 −0 Original line number Diff line number Diff line Loading @@ -32,5 +32,7 @@ #define RPMH_PKA_CLK 23 #define RPMH_HWKM_CLK 24 #define RPMH_QPIC_CLK 25 #define RPMH_DIV_CLK1 26 #define RPMH_DIV_CLK1_A 27 #endif