Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2674235f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:
 "We haven't seen a whole lot of fixes for the first two weeks since the
  merge window, but here is the batch that we have at the moment.

  Nothing sticks out as particularly bad or scary, it's mostly a handful
  of smaller fixes to several platforms. The Uniphier reset controller
  changes could probably have been delayed to 4.10, but they're not
  scary and just plumbing up driver changes that went in during the
  merge window.

  We're also adding another maintainer to Marvell Berlin platforms, to
  help out when Sebastian is too busy. Yay teamwork!"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: imx: mach-imx6q: Fix the PHY ID mask for AR8031
  ARM: dts: vf610: fix IRQ flag of global timer
  ARM: imx: gpc: Fix the imx_gpc_genpd_init() error path
  ARM: imx: gpc: Initialize all power domains
  arm64: dts: Updated NAND DT properties for NS2 SVK
  arm64: dts: uniphier: change MIO node to SD control node
  ARM: dts: uniphier: change MIO node to SD control node
  reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs
  arm64: uniphier: select ARCH_HAS_RESET_CONTROLLER
  ARM: uniphier: select ARCH_HAS_RESET_CONTROLLER
  arm64: dts: Add timer erratum property for LS2080A and LS1043A
  arm64: dts: rockchip: remove the abuse of keep-power-in-suspend
  ARM: multi_v7_defconfig: Enable Intel e1000e driver
  MAINTAINERS: add myself as Marvell berlin SoC maintainer
  bus: qcom-ebi2: depend on ARCH_QCOM or COMPILE_TEST
  ARM: dts: fix the SD card on the Snowball
  arm64: dts: rockchip: remove always-on and boot-on from vcc_sd
  arm64: dts: marvell: fix clocksource for CP110 master SPI0
  ARM: mvebu: Select corediv clk for all mvebu v7 SoC
parents 2a290036 b70e8beb

Documentation/devicetree/bindings/reset/uniphier-reset.txt

+31 −31
Original line number Original line Diff line number Diff line
@@ -6,25 +6,25 @@ System reset 




Required properties:

Required properties:

- compatible: should be one of the following:

- compatible: should be one of the following:

    "socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.

    "socionext,uniphier-sld3-reset" - for sLD3 SoC.

    "socionext,uniphier-ld4-reset"  - for PH1-LD4 SoC.

    "socionext,uniphier-ld4-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.

    "socionext,uniphier-pro4-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.

    "socionext,uniphier-sld8-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.

    "socionext,uniphier-pro5-reset" - for Pro5 SoC.

    "socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.

    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.

    "socionext,uniphier-ld11-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.

    "socionext,uniphier-ld20-reset" - for LD20 SoC.

- #reset-cells: should be 1.

- #reset-cells: should be 1.





Example:

Example:





	sysctrl@61840000 {

	sysctrl@61840000 {

		compatible = "socionext,uniphier-ld20-sysctrl",

		compatible = "socionext,uniphier-ld11-sysctrl",

			     "simple-mfd", "syscon";

			     "simple-mfd", "syscon";

		reg = <0x61840000 0x4000>;

		reg = <0x61840000 0x4000>;





		reset {

		reset {

			compatible = "socionext,uniphier-ld20-reset";

			compatible = "socionext,uniphier-ld11-reset";

			#reset-cells = <1>;

			#reset-cells = <1>;

		};

		};
@@ -32,30 +32,30 @@ Example: 
	};

	};









Media I/O (MIO) reset

Media I/O (MIO) reset, SD reset

---------------------

-------------------------------





Required properties:

Required properties:

- compatible: should be one of the following:

- compatible: should be one of the following:

    "socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.

    "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.

    "socionext,uniphier-ld4-mio-reset"  - for PH1-LD4 SoC.

    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.

    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.

    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.

    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC.

    "socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.

    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.

    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.

    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC.

- #reset-cells: should be 1.

- #reset-cells: should be 1.





Example:

Example:





	mioctrl@59810000 {

	mioctrl@59810000 {

		compatible = "socionext,uniphier-ld20-mioctrl",

		compatible = "socionext,uniphier-ld11-mioctrl",

			     "simple-mfd", "syscon";

			     "simple-mfd", "syscon";

		reg = <0x59810000 0x800>;

		reg = <0x59810000 0x800>;





		reset {

		reset {

			compatible = "socionext,uniphier-ld20-mio-reset";

			compatible = "socionext,uniphier-ld11-mio-reset";

			#reset-cells = <1>;

			#reset-cells = <1>;

		};

		};
@@ -68,24 +68,24 @@ Peripheral reset 




Required properties:

Required properties:

- compatible: should be one of the following:

- compatible: should be one of the following:

    "socionext,uniphier-ld4-peri-reset"  - for PH1-LD4 SoC.

    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.

    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.

    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.

    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.

    "socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.

    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.

    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.

    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC.

- #reset-cells: should be 1.

- #reset-cells: should be 1.





Example:

Example:





	perictrl@59820000 {

	perictrl@59820000 {

		compatible = "socionext,uniphier-ld20-perictrl",

		compatible = "socionext,uniphier-ld11-perictrl",

			     "simple-mfd", "syscon";

			     "simple-mfd", "syscon";

		reg = <0x59820000 0x200>;

		reg = <0x59820000 0x200>;





		reset {

		reset {

			compatible = "socionext,uniphier-ld20-peri-reset";

			compatible = "socionext,uniphier-ld11-peri-reset";

			#reset-cells = <1>;

			#reset-cells = <1>;

		};

		};

MAINTAINERS

+1 −0
Original line number Original line Diff line number Diff line
@@ -1442,6 +1442,7 @@ F: drivers/cpufreq/mvebu-cpufreq.c 
F:	arch/arm/configs/mvebu_*_defconfig

F:	arch/arm/configs/mvebu_*_defconfig





ARM/Marvell Berlin SoC support

ARM/Marvell Berlin SoC support

M:	Jisheng Zhang <jszhang@marvell.com>

M:	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

M:	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

S:	Maintained

arch/arm/boot/dts/ste-snowball.dts

+13 −2
Original line number Original line Diff line number Diff line
@@ -239,14 +239,25 @@ 
			arm,primecell-periphid = <0x10480180>;

			arm,primecell-periphid = <0x10480180>;

			max-frequency = <100000000>;

			max-frequency = <100000000>;

			bus-width = <4>;

			bus-width = <4>;

			cap-sd-highspeed;

			cap-mmc-highspeed;

			cap-mmc-highspeed;

			sd-uhs-sdr12;

			sd-uhs-sdr25;

			/* All direction control is used */

			st,sig-dir-cmd;

			st,sig-dir-dat0;

			st,sig-dir-dat2;

			st,sig-dir-dat31;

			st,sig-pin-fbclk;

			full-pwr-cycle;

			vmmc-supply = <&ab8500_ldo_aux3_reg>;

			vmmc-supply = <&ab8500_ldo_aux3_reg>;

			vqmmc-supply = <&vmmci>;

			vqmmc-supply = <&vmmci>;

			pinctrl-names = "default", "sleep";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&sdi0_default_mode>;

			pinctrl-0 = <&sdi0_default_mode>;

			pinctrl-1 = <&sdi0_sleep_mode>;

			pinctrl-1 = <&sdi0_sleep_mode>;





			cd-gpios  = <&gpio6 26 GPIO_ACTIVE_LOW>; // 218

			/* GPIO218 MMC_CD */

			cd-gpios  = <&gpio6 26 GPIO_ACTIVE_LOW>;





			status = "okay";

			status = "okay";

		};

		};
@@ -549,7 +560,7 @@ 
					/* VMMCI level-shifter enable */

					/* VMMCI level-shifter enable */

					snowball_cfg3 {

					snowball_cfg3 {

						pins = "GPIO217_AH12";

						pins = "GPIO217_AH12";

						ste,config = <&gpio_out_lo>;

						ste,config = <&gpio_out_hi>;

					};

					};

					/* VMMCI level-shifter voltage select */

					/* VMMCI level-shifter voltage select */

					snowball_cfg4 {

					snowball_cfg4 {

arch/arm/boot/dts/uniphier-pro5.dtsi

+2 −2
Original line number Original line Diff line number Diff line
@@ -184,11 +184,11 @@ 
};

};





&mio_clk {

&mio_clk {

	compatible = "socionext,uniphier-pro5-mio-clock";

	compatible = "socionext,uniphier-pro5-sd-clock";

};

};





&mio_rst {

&mio_rst {

	compatible = "socionext,uniphier-pro5-mio-reset";

	compatible = "socionext,uniphier-pro5-sd-reset";

};

};





&peri_clk {

&peri_clk {

arch/arm/boot/dts/uniphier-pxs2.dtsi

+2 −2
Original line number Original line Diff line number Diff line
@@ -197,11 +197,11 @@ 
};

};





&mio_clk {

&mio_clk {

	compatible = "socionext,uniphier-pxs2-mio-clock";

	compatible = "socionext,uniphier-pxs2-sd-clock";

};

};





&mio_rst {

&mio_rst {

	compatible = "socionext,uniphier-pxs2-mio-reset";

	compatible = "socionext,uniphier-pxs2-sd-reset";

};

};





&peri_clk {

&peri_clk {