Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 26738224 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add support for USB secondary clocks for YUPIK IOT"

parents 782b26e6 1bd678c3

qcom/yupik-iot-qrd.dtsi

+5 −7
Original line number Diff line number Diff line
@@ -21,13 +21,7 @@ 
		<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,

		<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,

		<GCC_PCIE_THROTTLE_CORE_CLK>, <GCC_THROTTLE_PCIE_AHB_CLK>,

		<GCC_AGGRE_USB3_SEC_AXI_CLK>, <GCC_CFG_NOC_USB3_SEC_AXI_CLK>,

		<GCC_USB30_SEC_MASTER_CLK>, <GCC_USB30_SEC_MASTER_CLK_SRC>,

		<GCC_USB30_SEC_MOCK_UTMI_CLK>, <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>,

		<GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>,

		<GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>,

		<GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>,

		<GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,

		<GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,

		<GCC_AGGRE_NOC_PCIE_TBU_CLK>, <GCC_PCIE_CLKREF_EN>;

};
@@ -38,3 +32,7 @@ 
&gcc_pcie_1_gdsc {

	status = "disabled";

};



&gcc_usb30_sec_gdsc {

	status = "ok";

};

qcom/yupik-iot.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -24,3 +24,7 @@ 
&gcc_pcie_1_gdsc {

	status = "ok";

};



&gcc_usb30_sec_gdsc {

	status = "ok";

};