Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2620f5e5 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: add display DT node for Holi target" into display-kernel.lnx.5.4

parents 1b7f8726 1314f595

display/holi-sde-display-cdp.dtsi

0 → 100644
+21 −0
Original line number Diff line number Diff line 
#include "holi-sde-display.dtsi"



&dsi_rm69299_visionox_amoled_video {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <4095>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-te-gpio = <&tlmm 23 0>;

	qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;

};



&dsi_sim_vid {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;

};



&sde_dsi {

	qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>;

};

display/holi-sde-display-mtp.dtsi

0 → 100644
+21 −0
Original line number Diff line number Diff line 
#include "holi-sde-display.dtsi"



&dsi_rm69299_visionox_amoled_video {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,mdss-dsi-bl-min-level = <1>;

	qcom,mdss-dsi-bl-max-level = <4095>;

	qcom,mdss-brightness-max-level = <255>;

	qcom,platform-te-gpio = <&tlmm 23 0>;

	qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;

};



&dsi_sim_vid {

	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

	qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;

};



&sde_dsi {

	qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>;

};

display/holi-sde-display.dtsi

0 → 100644
+133 −0
Original line number Diff line number Diff line 
#include "dsi-panel-sim-video.dtsi"

#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi"

#include <dt-bindings/clock/mdss-10nm-pll-clk.h>



&pm6150l_gpios {

	disp_pins {

		disp_pins_default: disp_pins_default {

			pins = "gpio9";

			function = "func1";

			qcom,drive-strength = <2>;

			power-source = <1>;

			bias-disable;

			output-low;

		};

	};

};



&soc {

	dsi_panel_pwr_supply: dsi_panel_pwr_supply {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <1800000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};



		qcom,panel-supply-entry@1 {

			reg = <1>;

			qcom,supply-name = "vdd";

			qcom,supply-min-voltage = <3000000>;

			qcom,supply-max-voltage = <3000000>;

			qcom,supply-enable-load = <857000>;

			qcom,supply-disable-load = <0>;

			qcom,supply-post-on-sleep = <0>;

		};



		qcom,panel-supply-entry@2 {

			reg = <2>;

			qcom,supply-name = "lab";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

		};



		qcom,panel-supply-entry@3 {

			reg = <3>;

			qcom,supply-name = "ibb";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

			qcom,supply-post-on-sleep = <20>;

		};

	};



	sde_dsi: qcom,dsi-display-primary {

		compatible = "qcom,dsi-display";

		label = "primary";



		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;



		clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi_phy0 PCLK_MUX_0_CLK>,

			 <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 PCLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";



		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_te_active &disp_pins_default>;

		pinctrl-1 = <&sde_te_suspend>;



		qcom,platform-te-gpio = <&tlmm 23 0>;

		qcom,panel-te-source = <0>;



		vddio-supply = <&L1E>;

		vdd-supply = <&L8A>;



		lab-supply = <&ab_vreg>;

		ibb-supply = <&ibb_vreg>;



		qcom,mdp = <&mdss_mdp>;

		qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>;

	};

};



&mdss_mdp {

	connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dsi>;

};



&dsi_sim_vid {

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01

				01 01 02 04 00 06 06];

			qcom,display-topology = <1 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};



&dsi_rm69299_visionox_amoled_video {

	qcom,mdss-dsi-panel-status-check-mode = "reg_read";

	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];

	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";

	qcom,mdss-dsi-panel-status-value = <0x9c>;

	qcom,mdss-dsi-panel-on-check-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,mdss-dsi-t-clk-post = <0x0E>;

	qcom,mdss-dsi-t-clk-pre = <0x31>;

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08

							08 05 02 04 00];

			qcom,display-topology = <1 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};

display/holi-sde.dtsi

0 → 100644
+376 −0
Original line number Diff line number Diff line 
#include <dt-bindings/clock/mdss-10nm-pll-clk.h>



&soc {

	mdss_mdp: qcom,mdss_mdp@5e00000 {

		compatible = "qcom,sde-kms";

		reg = <0x05e00000 0x8f030>,

		      <0x05eb0000 0x2008>,

		      <0x05e8f000 0x030>;

		reg-names = "mdp_phys",

			"vbif_phys",

			"sid_phys";



		clocks =

			<&gcc GCC_DISP_AHB_CLK>,

			<&gcc GCC_DISP_HF_AXI_CLK>,

			<&gcc GCC_DISP_THROTTLE_CORE_CLK>,

			<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,

			<&dispcc DISP_CC_MDSS_AHB_CLK>,

			<&dispcc DISP_CC_MDSS_MDP_CLK>,

			<&dispcc DISP_CC_MDSS_VSYNC_CLK>,

			<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

			<&dispcc DISP_CC_MDSS_ROT_CLK>;

		clock-names = "gcc_iface", "gcc_bus", "throttle_clk",

				 "div_clk",

				"iface_clk", "core_clk", "vsync_clk",

				"lut_clk", "rot_clk";

		clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>;

		clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000

					560000000>;



		sde-vdd-supply = <&mdss_core_gdsc>;



		/* interrupt config */

		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <1>;



		#power-domain-cells = <0>;



		/* hw blocks */

		qcom,sde-off = <0x1000>;

		qcom,sde-len = <0x494>;



		qcom,sde-ctl-off = <0x2000>;

		qcom,sde-ctl-size = <0x1dc>;

		qcom,sde-ctl-display-pref = "primary";



		qcom,sde-mixer-off = <0x45000>;

		qcom,sde-mixer-size = <0x320>;

		qcom,sde-mixer-display-pref = "primary";



		qcom,sde-dspp-top-off = <0x1300>;

		qcom,sde-dspp-top-size = <0x80>;

		qcom,sde-dspp-off = <0x55000>;

		qcom,sde-dspp-size = <0x1800>;



		qcom,sde-intf-off = <0x0 0x6b800>;

		qcom,sde-intf-size = <0x2c0>;

		qcom,sde-intf-type = "none", "dsi";

		qcom,sde-intf-tear-irq-off = <0 0x6e800>;



		qcom,sde-pp-off = <0x71000>;

		qcom,sde-pp-size = <0xd4>;



		qcom,sde-dsc-off = <0x81000>;

		qcom,sde-dsc-size = <0x140>;



		qcom,sde-dither-off = <0x30e0>;

		qcom,sde-dither-version = <0x00010000>;

		qcom,sde-dither-size = <0x20>;



		qcom,sde-sspp-type = "vig", "dma";



		qcom,sde-sspp-off = <0x5000 0x25000>;

		qcom,sde-sspp-src-size = <0x1f8>;



		qcom,sde-sspp-xin-id = <0 1>;

		qcom,sde-sspp-excl-rect = <1 1>;

		qcom,sde-sspp-smart-dma-priority = <2 1>;

		qcom,sde-smart-dma-rev = "smart_dma_v2p5";



		qcom,sde-mixer-pair-mask = <0>;

		qcom,sde-mixer-stage-base-layer;



		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98

						0xb0 0xc8 0xe0 0xf8 0x110>;



		qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>;



		qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>;



		/* offsets are relative to "mdp_phys + qcom,sde-off */

		qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>;

		qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>;

		qcom,sde-sspp-csc-off = <0x1a00>;

		qcom,sde-csc-type = "csc-10bit";

		qcom,sde-qseed-sw-lib-rev = "qseedv3lite";

		qcom,sde-qseed-scalar-version = <0x3000>;

		qcom,sde-sspp-qseed-off = <0xa00>;

		qcom,sde-sspp-linewidth = <2160>;

		qcom,sde-vig-sspp-linewidth = <4096>;

		qcom,sde-scaling-linewidth = <2560>;

		qcom,sde-mixer-linewidth = <2048>;

		qcom,sde-mixer-blendstages = <0x4>;

		qcom,sde-highest-bank-bit = <0x0 0x1>;

		qcom,sde-ubwc-version = <0x200>;

		qcom,sde-ubwc-swizzle = <0x6>;

		qcom,sde-ubwc-bw-calc-version = <0x1>;

		qcom,sde-ubwc-static = <0x1e>;

		qcom,sde-macrotile-mode = <0x0>;

		qcom,sde-panic-per-pipe;

		qcom,sde-has-cdp;

		qcom,sde-has-dim-layer;

		qcom,sde-has-idle-pc;

		qcom,sde-max-bw-low-kbps = <5200000>;

		qcom,sde-max-bw-high-kbps = <6200000>;

		qcom,sde-min-core-ib-kbps = <2500000>;

		qcom,sde-min-llcc-ib-kbps = <0>;

		qcom,sde-min-dram-ib-kbps = <1600000>;

		qcom,sde-dram-channels = <1>;

		qcom,sde-num-nrt-paths = <0>;



		qcom,sde-vbif-off = <0>;

		qcom,sde-vbif-size = <0x2008>;

		qcom,sde-vbif-id = <0>;

		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;

		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;



		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;

		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;



		qcom,sde-qos-refresh-rates = <60 120>;

		qcom,sde-danger-lut = <0xffff 0xffff 0x0

			0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0

			0x0 0x3ffff 0x3ffff>;



		qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>,

					<0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>;



		qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;

		qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;

		qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;

		qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;

		qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;



		qcom,sde-cdp-setting = <1 1>, <1 0>;



		qcom,sde-qos-cpu-mask = <0x3>;

		qcom,sde-qos-cpu-dma-latency = <300>;

		qcom,sde-qos-cpu-irq-latency = <300>;





		qcom,sde-secure-sid-mask = <0x821>;

		qcom,sde-num-mnoc-ports = <1>;

		qcom,sde-axi-bus-width = <32>;



		/* data and reg bus scale settings */

		interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>,

				<&bimc MASTER_AMPSS_M0

					&config_noc SLAVE_DISPLAY_CFG>;

		interconnect-names = "qcom,sde-data-bus0",

				"qcom,sde-reg-bus";

		qcom,sde-reg-bus,vectors-KBps = <0 0>,

				<0 76800>,

				<0 150000>,

				<0 300000>;



		qcom,sde-sspp-vig-blocks {

			qcom,sde-vig-csc-off = <0x1a00>;

			qcom,sde-vig-qseed-off = <0xa00>;

			qcom,sde-vig-qseed-size = <0xa0>;

		};



		qcom,sde-dspp-blocks {

			qcom,sde-dspp-igc = <0x0 0x00030001>;

			qcom,sde-dspp-hsic = <0x800 0x00010007>;

			qcom,sde-dspp-memcolor = <0x880 0x00010007>;

			qcom,sde-dspp-hist = <0x800 0x00010007>;

			qcom,sde-dspp-sixzone= <0x900 0x00010007>;

			qcom,sde-dspp-vlut = <0xa00 0x00010008>;

			qcom,sde-dspp-pcc = <0x1700 0x00040000>;

			qcom,sde-dspp-gc = <0x17c0 0x00010008>;

			qcom,sde-dspp-dither = <0x82c 0x00010007>;

		};



		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "sde-vdd";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_rotator: qcom,mdss_rotator {

		status = "disabled";

		compatible = "qcom,sde_rotator";

		reg = <0x5e00000 0xac000>,

			<0x5eb0000 0x2008>;



		reg-names = "mdp_phys",

				"rot_vbif_phys";



		#list-cells = <1>;

		qcom,mdss-rot-mode = <1>;

		rot-vdd-supply = <&mdss_core_gdsc>;

		qcom,supply-names = "rot-vdd";



		clocks =

			<&gcc GCC_DISP_AHB_CLK>,

			<&dispcc DISP_CC_MDSS_AHB_CLK>,

			<&dispcc DISP_CC_MDSS_ROT_CLK>;

		clock-names = "gcc_iface",

			"iface_clk", "rot_clk";



		interrupt-parent = <&mdss_mdp>;

		interrupts = <2 0>;



		power-domains = <&mdss_mdp>;



		interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>,

				<&bimc MASTER_AMPSS_M0

					&config_noc SLAVE_DISPLAY_CFG>;

		interconnect-names = "qcom,sde-data-bus0",

				"qcom,sde-reg-bus";

		qcom,sde-reg-bus,vectors-KBps = <0 0>,

				<0 76800>;



		/*Offline rotator RT setting */

		qcom,mdss-rot-parent = <&mdss_mdp 0>;

		qcom,mdss-rot-xin-id = <10 11>;



		/* Offline rotator QoS setting */

		qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;

		qcom,mdss-rot-cdp-setting = <1 1>;

		qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;

		qcom,mdss-rot-danger-lut = <0x0 0x0>;

		qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;



		qcom,mdss-default-ot-rd-limit = <32>;

		qcom,mdss-default-ot-wr-limit = <32>;



		qcom,mdss-sbuf-headroom = <20>;



		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {

			compatible = "qcom,smmu_sde_rot_unsec";

			iommus = <&apps_smmu 0x83C 0x0>;

			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;

			qcom,iommu-faults = "non-fatal";

		};



		smmu_rot_sec: qcom,smmu_rot_sec_cb {

			compatible = "qcom,smmu_sde_rot_sec";

			iommus = <&apps_smmu 0x83D 0x0>;

			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-vmid = <0xa>;

		};

	};



	mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 {

		compatible = "qcom,dsi-ctrl-hw-v2.4";

		label = "dsi-ctrl-0";

		cell-index = <0>;

		frame-threshold-time-us = <1000>;

		reg = <0x05e94000 0x400>,

			<0x05f08000 0x4>;

		reg-names = "dsi_ctrl", "disp_cc_base";

		interrupt-parent = <&mdss_mdp>;

		interrupts = <4 0>;

		vdda-1p2-supply = <&L22A>;

		refgen-supply = <&refgen>;

		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,

			<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,

			<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

			<&dispcc DISP_CC_MDSS_PCLK0_CLK>,

			<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,

			<&dispcc DISP_CC_MDSS_ESC0_CLK>;

		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",

				"pixel_clk", "pixel_clk_rcg", "esc_clk";



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 {

		compatible = "qcom,dsi-phy-v3.0";

		label = "dsi-phy-0";

		cell-index = <0>;

		#clock-cells = <1>;

		reg = <0x05e94400 0x800>,

		      <0x05e94a00 0x1e0>,

		      <0x05f01004 0x8>,

		      <0x05e94200 0x100>;

		reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";

		pll-label = "dsi_pll_10nm";

		vdda-0p9-supply = <&S5A_LEVEL>;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";

		qcom,platform-strength-ctrl = [55 03

						55 03

						55 03

						55 03

						55 00];

		qcom,platform-lane-config = [00 00 00 00

						00 00 00 00

						00 00 00 00

						00 00 00 00

						00 00 00 80];

		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];

		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage =

					<RPMH_REGULATOR_LEVEL_NOM>;

				qcom,supply-max-voltage =

					<RPMH_REGULATOR_LEVEL_TURBO_L1>;

				qcom,supply-off-min-voltage =

					<RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {

		compatible = "qcom,smmu_sde_unsec";

		iommus = <&apps_smmu 0x820 0x2>;

		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;

		qcom,iommu-faults = "non-fatal";

		qcom,iommu-earlymap; /* for cont-splash */

	};



	smmu_sde_sec: qcom,smmu_sde_sec_cb {

		compatible = "qcom,smmu_sde_sec";

		iommus = <&apps_smmu 0x821 0x0>;

		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;

		qcom,iommu-faults = "non-fatal";

		qcom,iommu-vmid = <0xa>;

	};



};