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Commit 26150aa9 authored by Jonathan Austin's avatar Jonathan Austin Committed by Russell King
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ARM: 8602/1: factor out CSSELR/CCSIDR operations that use cp15 directly 



Currently we use raw cp15 operations to access the cache setup data.

This patch abstracts the CSSELR and CCSIDR accessors out to a header so
that the implementation for them can be switched out as we do with other
cpu/cachetype operations.

Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: default avatarAndras Szemzo <sza@esh.hu>
Tested-by: default avatarJoachim Eastwood <manabian@gmail.com>
Tested-by: default avatarAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 5a0e0691

arch/arm/include/asm/cachetype.h

+24 −0
Original line number Original line Diff line number Diff line
@@ -56,4 +56,28 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask) 
	       (~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);

	       (~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);

}

}





#define CSSELR_ICACHE	1

#define CSSELR_DCACHE	0



#define CSSELR_L1	(0 << 1)

#define CSSELR_L2	(1 << 1)

#define CSSELR_L3	(2 << 1)

#define CSSELR_L4	(3 << 1)

#define CSSELR_L5	(4 << 1)

#define CSSELR_L6	(5 << 1)

#define CSSELR_L7	(6 << 1)



static inline void set_csselr(unsigned int cache_selector)

{

	asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));

}



static inline unsigned int read_ccsidr(void)

{

	unsigned int val;



	asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));

	return val;

}



#endif
 
#endif

arch/arm/kernel/setup.c

+2 −5
Original line number Original line Diff line number Diff line
@@ -290,12 +290,9 @@ static int cpu_has_aliasing_icache(unsigned int arch) 
	/* arch specifies the register format */

	/* arch specifies the register format */

	switch (arch) {

	switch (arch) {

	case CPU_ARCH_ARMv7:

	case CPU_ARCH_ARMv7:

		asm("mcr	p15, 2, %0, c0, c0, 0 @ set CSSELR"

		set_csselr(CSSELR_ICACHE | CSSELR_L1);

		    : /* No output operands */

		    : "r" (1));

		isb();

		isb();

		asm("mrc	p15, 1, %0, c0, c0, 0 @ read CCSIDR"

		id_reg = read_ccsidr();

		    : "=r" (id_reg));

		line_size = 4 << ((id_reg & 0x7) + 2);

		line_size = 4 << ((id_reg & 0x7) + 2);

		num_sets = ((id_reg >> 13) & 0x7fff) + 1;

		num_sets = ((id_reg >> 13) & 0x7fff) + 1;

		aliasing_icache = (line_size * num_sets) > PAGE_SIZE;

		aliasing_icache = (line_size * num_sets) > PAGE_SIZE;