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Commit 2572f00d authored by Joshua Henderson's avatar Joshua Henderson Committed by Ralf Baechle
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MIPS: Add support for PIC32MZDA platform 



This adds support for the Microchip PIC32 MIPS microcontroller with the
specific variant PIC32MZDA. PIC32MZDA is based on the MIPS m14KEc core
and boots using device tree.

This includes an early pin setup and early clock setup needed prior to
device tree being initialized. In additon, an interface is provided to
synchronize access to registers shared across several peripherals.

Signed-off-by: default avatarJoshua Henderson <joshua.henderson@microchip.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12097/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9b9c2cd4

arch/mips/Kbuild.platforms

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ platforms += mti-malta 
platforms += mti-sead3

platforms += netlogic

platforms += paravirt

platforms += pic32

platforms += pistachio

platforms += pmcs-msp71xx

platforms += pnx833x

arch/mips/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -481,6 +481,14 @@ config MIPS_MALTA 
	  This enables support for the MIPS Technologies Malta evaluation

	  board.



config MACH_PIC32

	bool "Microchip PIC32 Family"

	help

	  This enables support for the Microchip PIC32 family of platforms.



	  Microchip PIC32 is a family of general-purpose 32 bit MIPS core

	  microcontrollers.



config MIPS_SEAD3

	bool "MIPS SEAD3 board"

	select BOOT_ELF32
@@ -980,6 +988,7 @@ source "arch/mips/jazz/Kconfig" 
source "arch/mips/jz4740/Kconfig"

source "arch/mips/lantiq/Kconfig"

source "arch/mips/lasat/Kconfig"

source "arch/mips/pic32/Kconfig"

source "arch/mips/pistachio/Kconfig"

source "arch/mips/pmcs-msp71xx/Kconfig"

source "arch/mips/ralink/Kconfig"

arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h

0 → 100644
+32 −0
Original line number Diff line number Diff line 
/*

 * Joshua Henderson <joshua.henderson@microchip.com>

 * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#ifndef __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H

#define __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H



/*

 * CPU feature overrides for PIC32 boards

 */

#ifdef CONFIG_CPU_MIPS32

#define cpu_has_vint		1

#define cpu_has_veic		0

#define cpu_has_tlb		1

#define cpu_has_4kex		1

#define cpu_has_4k_cache	1

#define cpu_has_fpu		0

#define cpu_has_counter		1

#define cpu_has_llsc		1

#define cpu_has_nofpuex		0

#define cpu_icache_snoops_remote_store 1

#endif



#ifdef CONFIG_CPU_MIPS64

#error This platform does not support 64bit.

#endif



#endif /* __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mach-pic32/irq.h

0 → 100644
+22 −0
Original line number Diff line number Diff line 
/*

 * Joshua Henderson <joshua.henderson@microchip.com>

 * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.

 *

 * This program is free software; you can distribute it and/or modify it

 * under the terms of the GNU General Public License (Version 2) as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * for more details.

 */

#ifndef __ASM_MACH_PIC32_IRQ_H

#define __ASM_MACH_PIC32_IRQ_H



#define NR_IRQS	256

#define MIPS_CPU_IRQ_BASE 0



#include_next <irq.h>



#endif /* __ASM_MACH_PIC32_IRQ_H */

arch/mips/include/asm/mach-pic32/pic32.h

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+44 −0
Original line number Diff line number Diff line 
/*

 * Joshua Henderson <joshua.henderson@microchip.com>

 * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.

 *

 * This program is free software; you can distribute it and/or modify it

 * under the terms of the GNU General Public License (Version 2) as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * for more details.

 */

#ifndef _ASM_MACH_PIC32_H

#define _ASM_MACH_PIC32_H



#include <linux/io.h>



/*

 * PIC32 register offsets for SET/CLR/INV where supported.

 */

#define PIC32_CLR(_reg)		((_reg) + 0x04)

#define PIC32_SET(_reg)		((_reg) + 0x08)

#define PIC32_INV(_reg)		((_reg) + 0x0C)



/*

 * PIC32 Base Register Offsets

 */

#define PIC32_BASE_CONFIG	0x1f800000

#define PIC32_BASE_OSC		0x1f801200

#define PIC32_BASE_RESET	0x1f801240

#define PIC32_BASE_PPS		0x1f801400

#define PIC32_BASE_UART		0x1f822000

#define PIC32_BASE_PORT		0x1f860000

#define PIC32_BASE_DEVCFG2	0x1fc4ff44



/*

 * Register unlock sequence required for some register access.

 */

void pic32_syskey_unlock_debug(const char *fn, const ulong ln);

#define pic32_syskey_unlock()	\

	pic32_syskey_unlock_debug(__func__, __LINE__)



#endif /* _ASM_MACH_PIC32_H */