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Commit 2561b292 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Add a3xx probe function 



Add a target specific function for a3xx probe and create a helper
function to set up the register offset array.

Change-Id: Ic0dedbad2f8f54ee2635da3cb8256fce531ab8dd
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent c96f0216

drivers/gpu/msm/adreno.c

+1 −9
Original line number Diff line number Diff line
@@ -1458,21 +1458,13 @@ int adreno_target_probe(struct platform_device *pdev, 
{

	struct adreno_device *adreno_dev = &device_3d0;

	struct adreno_gpudev *gpudev = gpucore->gpudev;

	int i;



	memset(adreno_dev, 0, sizeof(*adreno_dev));



	adreno_dev->gpucore = gpucore;

	adreno_dev->chipid = chipid;



	/*

	 * Initialize uninitialzed gpu registers, only needs to be done once

	 * Make all offsets that are not initialized to ADRENO_REG_UNUSED

	 */

	for (i = 0; i < ADRENO_REG_REGISTER_MAX; i++) {

		if (!gpudev->reg_offsets[i])

			gpudev->reg_offsets[i] = ADRENO_REG_UNUSED;

	}

	adreno_reg_offset_init(gpudev->reg_offsets);



	/* Do target specific identification */

	if (gpudev->platform_setup)

drivers/gpu/msm/adreno.h

+22 −0
Original line number Diff line number Diff line
@@ -1662,6 +1662,28 @@ static inline bool adreno_move_preempt_state(struct adreno_device *adreno_dev, 
	return (atomic_cmpxchg(&adreno_dev->preempt.state, old, new) == old);

}



/**

 * adreno_reg_offset_init - Helper function to initialize reg_offsets

 * @reg_offsets: Pointer to an array of register offsets

 *

 * Helper function to setup register_offsets for a target. Go through

 * and set ADRENO_REG_UNUSED for all unused entries in the list.

 */

static inline void adreno_reg_offset_init(u32 *reg_offsets)

{

	int i;



	/*

	 * Initialize uninitialzed gpu registers, only needs to be done once.

	 * Make all offsets that are not initialized to ADRENO_REG_UNUSED

	 */

	for (i = 0; i < ADRENO_REG_REGISTER_MAX; i++) {

		if (!reg_offsets[i])

			reg_offsets[i] = ADRENO_REG_UNUSED;

	}

}





void adreno_gmu_clear_and_unmask_irqs(struct adreno_device *adreno_dev);

void adreno_gmu_mask_and_clear_irqs(struct adreno_device *adreno_dev);

int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,

drivers/gpu/msm/adreno_a3xx.c

+18 −3
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 


#include <linux/firmware.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/slab.h>



#include "adreno.h"
@@ -567,10 +568,25 @@ static int _a3xx_pwron_fixup(struct adreno_device *adreno_dev) 
	return 0;

}



static void a3xx_platform_setup(struct adreno_device *adreno_dev)

static int a3xx_probe(struct platform_device *pdev,

		u32 chipid, const struct adreno_gpu_core *gpucore)

{

	struct adreno_device *adreno_dev;



	adreno_dev = (struct adreno_device *)

		of_device_get_match_data(&pdev->dev);



	memset(adreno_dev, 0, sizeof(*adreno_dev));



	adreno_dev->gpucore = gpucore;

	adreno_dev->chipid = chipid;



	adreno_reg_offset_init(gpucore->gpudev->reg_offsets);



	/* Set the GPU busy counter for frequency scaling */

	adreno_dev->perfctr_pwr_lo = A3XX_RBBM_PERFCTR_PWR_1_LO;



	return adreno_device_probe(pdev, adreno_dev);

}



static int a3xx_send_me_init(struct adreno_device *adreno_dev,
@@ -1406,8 +1422,7 @@ struct adreno_gpudev adreno_a3xx_gpudev = { 
	.perfcounters = &a3xx_perfcounters,

	.irq_handler = a3xx_irq_handler,

	.vbif_xin_halt_ctrl0_mask = A30X_VBIF_XIN_HALT_CTRL0_MASK,

	.probe = adreno_target_probe,

	.platform_setup = a3xx_platform_setup,

	.probe = a3xx_probe,

	.rb_start = a3xx_rb_start,

	.init = a3xx_init,

	.microcode_read = a3xx_microcode_read,