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Commit 24f9f5bb authored by Frank Wang's avatar Frank Wang Committed by Heiko Stuebner
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ARM: dts: rockchip: add usb nodes for rv1108 SoCs 



This patch adds usb otg/host controllers and phys nodes for RV1108 SoCs.

Signed-off-by: default avatarFrank Wang <frank.wang@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 45a7d2ca

arch/arm/boot/dts/rv1108.dtsi

+72 −1
Original line number Diff line number Diff line
@@ -289,8 +289,35 @@ 
	};



	grf: syscon@10300000 {

		compatible = "rockchip,rv1108-grf", "syscon";

		compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";

		reg = <0x10300000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		u2phy: usb2-phy@100 {

			compatible = "rockchip,rv1108-usb2phy";

			reg = <0x100 0x0c>;

			clocks = <&cru SCLK_USBPHY>;

			clock-names = "phyclk";

			#clock-cells = <0>;

			clock-output-names = "usbphy";

			rockchip,usbgrf = <&usbgrf>;

			status = "disabled";



			u2phy_otg: otg-port {

				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "otg-mux";

				#phy-cells = <0>;

				status = "disabled";

			};



			u2phy_host: host-port {

				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "linestate";

				#phy-cells = <0>;

				status = "disabled";

			};

		};

	};



	watchdog: wdt@10360000 {
@@ -380,6 +407,11 @@ 
		reg = <0x20060000 0x1000>;

	};



	usbgrf: syscon@202a0000 {

		compatible = "rockchip,rv1108-usbgrf", "syscon";

		reg = <0x202a0000 0x1000>;

	};



	cru: clock-controller@20200000 {

		compatible = "rockchip,rv1108-cru";

		reg = <0x20200000 0x1000>;
@@ -426,6 +458,45 @@ 
		status = "disabled";

	};



	usb_host_ehci: usb@30140000 {

		compatible = "generic-ehci";

		reg = <0x30140000 0x20000>;

		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_HOST0>, <&u2phy>;

		clock-names = "usbhost", "utmi";

		phys = <&u2phy_host>;

		phy-names = "usb";

		status = "disabled";

	};



	usb_host_ohci: usb@30160000 {

		compatible = "generic-ohci";

		reg = <0x30160000 0x20000>;

		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_HOST0>, <&u2phy>;

		clock-names = "usbhost", "utmi";

		phys = <&u2phy_host>;

		phy-names = "usb";

		status = "disabled";

	};



	usb_otg: usb@30180000 {

		compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",

			     "snps,dwc2";

		reg = <0x30180000 0x40000>;

		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_OTG>;

		clock-names = "otg";

		dr_mode = "otg";

		g-np-tx-fifo-size = <16>;

		g-rx-fifo-size = <280>;

		g-tx-fifo-size = <256 128 128 64 32 16>;

		g-use-dma;

		phys = <&u2phy_otg>;

		phy-names = "usb2-phy";

		status = "disabled";

	};



	gic: interrupt-controller@32010000 {

		compatible = "arm,gic-400";

		interrupt-controller;