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Commit 24f8b6eb authored by Veera Vegivada's avatar Veera Vegivada
Browse files

ARM: dts: msm: Add UFS support for SA8155

Add UFS host controller and UFS PHY (attached to embedded UFS card)
for SM8150 platform and SA8155.

Change-Id: I2f58f3bd2457fed0baaffa5233bbd2c92ec22c12
parent 6236ec35
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+25 −0
Original line number Diff line number Diff line
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qmp-v4";

	vdda-pll-supply = <&pm8150_2_l8>;
	vdda-phy-max-microamp = <87100>;
	vdda-pll-max-microamp = <18300>;

	status = "ok";
};

&ufshc_mem {
	vdd-hba-supply = <&ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm8150_1_l10>;
	vcc-voltage-level = <2950000 2960000>;
	vccq2-supply = <&pm8150_1_s4>;
	vcc-max-microamp = <750000>;
	vccq2-max-microamp = <750000>;

	qcom,vddp-ref-clk-supply = <&pm8150_2_l5>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	status = "ok";
};
+4 −0
Original line number Diff line number Diff line
@@ -68,3 +68,7 @@
&gpu_gx_gdsc {
	parent-supply = <&VDD_GFX_LEVEL>;
};

&ufsphy_mem {
	vdda-phy-supply = <&pm8150_2_l18>;
};
+140 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,npucc-sm8150.h>
#include <dt-bindings/clock/qcom,scc-sm8150.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -24,6 +25,7 @@
	memory { device_type = "memory"; reg = <0 0 0 0>; };

	aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
		serial0 = &uart2;
	};

@@ -934,6 +936,144 @@
	};


	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xda8>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_UFS_MEM_CLKREF_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		resets = <&ufshc_mem 0>;
		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x2500>,
			  <0x1d90000 0x8000>;
		reg-names = "ufs_mem", "ufs_ice";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		#reset-cells = <1>;

		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&gcc GCC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<37500000 300000000>,
			<0 0>,
			<0 0>,
			<37500000 300000000>,
			<37500000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;
		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
		interconnect-names = "ufs-ddr", "cpu-ufs";

		qcom,ufs-bus-bw,name = "ufshc_mem";
		qcom,ufs-bus-bw,num-cases = <26>;
		qcom,ufs-bus-bw,num-paths = <2>;
		qcom,ufs-bus-bw,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<0 0>, <0 0>,          /* No vote */
		<922 0>, <1000 0>,     /* PWM G1 */
		<1844 0>, <1000 0>,    /* PWM G2 */
		<3688 0>, <1000 0>,    /* PWM G3 */
		<7376 0>, <1000 0>,    /* PWM G4 */
		<1844 0>, <1000 0>,    /* PWM G1 L2 */
		<3688 0>, <1000 0>,    /* PWM G2 L2 */
		<7376 0>, <1000 0>,    /* PWM G3 L2 */
		<14752 0>, <1000 0>,   /* PWM G4 L2 */
		<127796 0>, <1000 0>,  /* HS G1 RA */
		<255591 0>, <1000 0>,  /* HS G2 RA */
		<2097152 0>, <102400 0>,  /* HS G3 RA */
		<4194304 0>, <204800 0>,  /* HS G4 RA */
		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
		<4194304 0>, <204800 0>, /* HS G3 RA L2 */
		<8388608 0>, <409600 0>, /* HS G4 RA L2 */
		<149422 0>, <1000 0>,  /* HS G1 RB */
		<298189 0>, <1000 0>,  /* HS G2 RB */
		<2097152 0>, <102400 0>,  /* HS G3 RB */
		<4194304 0>, <204800 0>,  /* HS G4 RB */
		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
		/* As UFS working in HS G3 RB L2 mode, aggregated
		 * bandwidth (AB) should take care of providing
		 * optimum throughput requested. However, as tested,
		 * in order to scale up CNOC clock, instantaneous
		 * bindwidth (IB) needs to be given a proper value too.
		 */
		<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
		<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
		<7643136 0>, <307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
		"MAX";

		reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;

		resets = <&gcc GCC_UFS_PHY_BCR>;
		reset-names = "rst";

		status = "disabled";
		qos0 {
			mask = <0xf0>;
			vote = <44>;
		};

		qos1 {
			mask = <0x0f>;
			vote = <44>;
		};
	};

	qupv3_id_1: geniqup@ac0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0x00ac0000 0x6000>;