Merge "ARM: dts: qcom: fix memory node address and enable scm driver" (24f21e99) · Commits · e / devices / android_kernel_fairphone_FP5

bindings/haven/qcom,hypervisor.yml

0 → 100644

+177 −0

Original line number	Diff line number	Diff line
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/haven/qcom,hypervisor.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Hypervisor node to define virtual devices and other services.

		maintainers:
		- Murali Nalajala <mnalajal@quicinc.com>

		description: \|+
		Top-level node named /hypervisor that describes virtual devices and other
		services.

		properties:
		compatible:
		oneOf:
		items:
		- const: qcom,haven-hypervisor-1.0
		- const: qcom,haven-hypervisor

		properties:
		"#address-cells":
		const: 2
		"#size-cells":
		description: must be 0, because capability IDs are not memory address
		ranges and do not have a size.
		const: 0


		required:
		- compatible
		- "#address-cells"
		- "#size-cells"


		description: \|+
		The VM Identification is a virtual node that conveys to the VM information
		about itself in the context of the hypervisor-based system and may be
		present as a child of the /hypervisor node

		properties:
		compatible:
		oneOf:
		description: \|+
		Must contain the VM-ID compatible string, which is provisionally
		specified as "qcom,haven-vm-id". This should be preceded by
		a string that specifies the VM ID API version, which is currently
		1.0, thus "qcom,haven-vm-id-1.0".
		items:
		- const: qcom,haven-vm-id-1.0
		- const: qcom,haven-vm-id

		properties:
		qcom,vendor:
		description: must contain the VM vendor string, for example: "Qualcomm".
		$ref: /schemas/types.yaml#/definitions/string

		qcom,vmid:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: must contain the hypervisor VMID of the VM, as
		a 32-bit value

		qcom,owner-vmid:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: Contains the hypervisor VMID of the VM’s owner. The owner
		is the VM that allocated and created the VM. VMs directly
		managed by the resource manager, such as the HLOS do not
		have an owner.

		qcom,image-name:
		$ref: /schemas/types.yaml#/definitions/string
		description: contains the VM image name string.

		qcom,swid:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: must contain the Qualcomm PIL software ID value.

		required:
		- compatible
		- qcom,vmid
		- qcom,owner-vmid


		description: \|+
		Resource Manager node which is required to communicate to Resource
		Manager VM using RM Message Queues.

		properties:
		compatible:
		oneOf:
		description:
		The resource manager RPC communicate link is required to be in the
		device-tree of a VM at boot, without it, a VM may be unable to
		communicate with the Resource Manager. Resource Manager VM can
		support implementation of various versions i.e 1.0 or 2.0

		items:
		- const: qcom,resource-manager-1-0
		- const: qcom,resource-manager
		- const: qcom,haven-message-queue
		- const: qcom,haven-capability

		interrupts:
		maxItems: 2

		reg:
		maxItems: 2

		qcom,is-full-duplex:
		$ref: /schemas/types.yaml#/definitions/flag
		description: This node is a pair of message queues i.e. Tx and Rx

		qcom,tx-message-size:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: maximum message size in bytes, >= 240 bytes for RM IPC

		qcom,tx-queue-depth:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: depth(size) of transmit queue in hypervisor

		qcom,rx-message-size:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: maximum message size in bytes, >= 240 bytes for RM IPC

		qcom,rx-queue-depth:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: depth(size) of receive queue in hypervisor

		qcom,console-dev:
		$ref: /schemas/types.yaml#/definitions/flag
		description: if set, the resource-manger will accept console logs
		from the VM

		qcom,free-irq-start:
		$ref: /schemas/types.yaml#/definitions/uint32
		description: first VIRQ number which is free for virtual interrupt
		use. Here SPI 0 = VIRQ 32.

		required:
		- compatible
		- interrupts
		- reg
		- qcom,is-full-duplex

		examples:
		- \|
		hypervisor {
		#address-cells = <2>;
		#size-cells = <0>;
		compatible = "qcom,haven-hypervisor-1.0", "qcom,haven-hypervisor",
		"simple-bus";
		name = "hypervisor";

		qcom,haven-vm {
		compatible = "qcom,haven-vm-id-1.0", "qcom,haven-vm-id";
		qcom,vendor = "Qualcomm Technologies, Inc.";
		qcom,vmid = <45>;
		qcom,owner-vmid = <3>;
		};

		qcom,resource-manager-rpc@0000000000000001 {
		compatible = "qcom,resource-manager-1-0", "qcom,resource-manager",
		"qcom,haven-message-queue", "qcom,haven-capability";
		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, /* TX full IRQ */
		<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; /* RX empty IRQ */
		reg = <0x00000000 0x00000000>, <0x00000000 0x00000001>;
		/* TX, RX cap ids */
		qcom,is-full-duplex;
		qcom,free-irq-start = <0>;
		qcom,tx-queue-depth = <8>;
		qcom,tx-message-size = <0xf0>;
		qcom,rx-queue-depth = <8>;
		qcom,rx-message-size = <0xf0>;
		};
		};

qcom/trustedvm.dtsi

+123 −31

Original line number	Diff line number	Diff line
		@@ -5,8 +5,18 @@
		#size-cells = <0x2>;
		interrupt-parent = <&vgic>;

		memory@28800000 {
		device_type = "memory";
		reg = <0x0 0x28800000 0x0 0x76f7000>; /* Temp S2 mapping */
		};

		qcom-mem-buf {
		compatible = "qcom,mem-buf";
		qcom,mem-buf-capabilities = "consumer";
		};

		chosen {
		bootargs = "root=/dev/ram rw init=/init console=hvc0 loglevel=8";
		bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8";
		linux,initrd-start = <0x2a900000>;
		linux,initrd-end = <0x2b100000>; /* 8 MB */
		kaslr-seed = <0xfeedbeef 0xc0def00d>;
		@@ -23,29 +33,62 @@
		enable-method = "psci";
		cpu-idle-states = <0x2>;
		};

		CPU1: cpu@100 {
		compatible = "arm,armv8";
		reg = <0x0 0x100>;
		device_type = "cpu";
		enable-method = "psci";
		cpu-idle-states = <0x2>;
		};

		vgic: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
		<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
		CPU2: cpu@200 {
		compatible = "arm,armv8";
		reg = <0x0 0x200>;
		device_type = "cpu";
		enable-method = "psci";
		cpu-idle-states = <0x2>;
		};

		psci {
		compatible = "arm,psci-1.0";
		method = "smc";
		CPU3: cpu@300 {
		compatible = "arm,armv8";
		reg = <0x0 0x300>;
		device_type = "cpu";
		enable-method = "psci";
		cpu-idle-states = <0x2>;
		};

		qcom-mem-buf {
		compatible = "qcom,mem-buf";
		qcom,mem-buf-capabilities = "consumer";
		CPU4: cpu@400 {
		compatible = "arm,armv8";
		reg = <0x0 0x400>;
		device_type = "cpu";
		enable-method = "psci";
		cpu-idle-states = <0x2>;
		};

		memory@28800000 {
		device_type = "memory";
		reg = <0x0 0x28800000 0x0 0x76f7000>; /* Temp S2 mapping */
		CPU5: cpu@500 {
		compatible = "arm,armv8";
		reg = <0x0 0x500>;
		device_type = "cpu";
		enable-method = "psci";
		cpu-idle-states = <0x2>;
		};

		CPU6: cpu@600 {
		compatible = "arm,armv8";
		reg = <0x0 0x600>;
		device_type = "cpu";
		enable-method = "psci";
		cpu-idle-states = <0x2>;
		};

		CPU7: cpu@700 {
		compatible = "arm,armv8";
		reg = <0x0 0x700>;
		device_type = "cpu";
		enable-method = "psci";
		cpu-idle-states = <0x2>;
		};
		};

		reserved_memory: reserved-memory {
		@@ -125,13 +168,14 @@
		#address-cells = <0x2>;
		#size-cells = <0x0>;
		base-address = <0x0 0xD0800000>;
		size-min = <0x0 0x8000000>; /* 128 MB */
		size-min = <0x0 0x76f7000>; /* 118 MB */
		};

		segments {
		/* offset and size */
		kernel = <0x0 0x8000 0x0 0x2000000>; /* 32 MB */
		dt = <0x0 0x7000000 0x0 0x4000>; /* 16 KB */
		kernel = <0x0 0x80000 0x0 0x1f80000>; /* 31MB */
		dt = <0x0 0x2000000 0x0 0x100000>; /* 1MB */
		ramdisk = <0x0 0x2100000 0x0 0x800000>; /* 8MB */
		};

		vcpus {
		@@ -149,14 +193,40 @@
		};
		};

		arch_timer: timer {
		compatible = "arm,armv8-timer";
		always-on;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
		/* Temporary node until RM dynamic overlay support present */
		hypervisor {
		#address-cells = <2>;
		#size-cells = <0>;
		compatible = "qcom,haven-hypervisor-1.0", "qcom,haven-hypervisor", "simple-bus";
		name = "hypervisor";

		qcom,haven-vm {
		compatible = "qcom,haven-vm-id-1.0", "qcom,haven-vm-id";
		qcom,vendor = "Qualcomm Technologies, Inc.";
		qcom,vmid = <45>;
		qcom,owner-vmid = <3>;
		};

		qcom,resource-manager-rpc@0000000000000001 {
		compatible = "qcom,resource-manager-1-0", "qcom,resource-manager", "qcom,haven-message-queue", "qcom,haven-capability";
		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, /* TX full IRQ */
		<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; /* RX empty IRQ */
		reg = <0x00000000 0x00000000>, <0x00000000 0x00000001>; /* TX, RX cap ids */
		qcom,is-full-duplex;
		qcom,free-irq-start = <0>;
		qcom,tx-queue-depth = <8>;
		qcom,tx-message-size = <0xf0>;
		qcom,rx-queue-depth = <8>;
		qcom,rx-message-size = <0xf0>;
		};
		};

		firmware: firmware {
		scm {
		compatible = "qcom,scm";
		};
		};

		soc: soc { };
		};

		@@ -181,6 +251,28 @@
		qcom,ee = <0>;
		};

		psci {
		compatible = "arm,psci-1.0";
		method = "smc";
		};

		vgic: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x17a00000 0x10000>, /* GICD */
		<0x17a60000 0x100000>; /* GICR * 8 */
		};

		arch_timer: timer {
		compatible = "arm,armv8-timer";
		always-on;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
		};

		/*
		* QUPv3 Instances
		* North 4 : SE 4