Loading drivers/gpu/msm/a6xx_reg.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -724,6 +724,7 @@ #define A6XX_UCHE_PERFCTR_UCHE_SEL_10 0xE26 #define A6XX_UCHE_PERFCTR_UCHE_SEL_10 0xE26 #define A6XX_UCHE_PERFCTR_UCHE_SEL_11 0xE27 #define A6XX_UCHE_PERFCTR_UCHE_SEL_11 0xE27 #define A6XX_UCHE_GBIF_GX_CONFIG 0xE3A #define A6XX_UCHE_GBIF_GX_CONFIG 0xE3A #define A6XX_UCHE_CMDQ_CONFIG 0xE3C /* SP registers */ /* SP registers */ #define A6XX_SP_ADDR_MODE_CNTL 0xAE01 #define A6XX_SP_ADDR_MODE_CNTL 0xAE01 Loading drivers/gpu/msm/adreno_a6xx.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -109,6 +109,7 @@ static u32 a650_pwrup_reglist[] = { A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, A6XX_UCHE_CMDQ_CONFIG, }; }; static u32 a615_pwrup_reglist[] = { static u32 a615_pwrup_reglist[] = { Loading Loading @@ -628,6 +629,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) if (adreno_is_a660(adreno_dev)) { if (adreno_is_a660(adreno_dev)) { kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1); kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1); kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); kgsl_regwrite(device, A6XX_UCHE_CMDQ_CONFIG, 0x90); } } if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV)) if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV)) Loading Loading
drivers/gpu/msm/a6xx_reg.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -724,6 +724,7 @@ #define A6XX_UCHE_PERFCTR_UCHE_SEL_10 0xE26 #define A6XX_UCHE_PERFCTR_UCHE_SEL_10 0xE26 #define A6XX_UCHE_PERFCTR_UCHE_SEL_11 0xE27 #define A6XX_UCHE_PERFCTR_UCHE_SEL_11 0xE27 #define A6XX_UCHE_GBIF_GX_CONFIG 0xE3A #define A6XX_UCHE_GBIF_GX_CONFIG 0xE3A #define A6XX_UCHE_CMDQ_CONFIG 0xE3C /* SP registers */ /* SP registers */ #define A6XX_SP_ADDR_MODE_CNTL 0xAE01 #define A6XX_SP_ADDR_MODE_CNTL 0xAE01 Loading
drivers/gpu/msm/adreno_a6xx.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -109,6 +109,7 @@ static u32 a650_pwrup_reglist[] = { A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, A6XX_UCHE_CMDQ_CONFIG, }; }; static u32 a615_pwrup_reglist[] = { static u32 a615_pwrup_reglist[] = { Loading Loading @@ -628,6 +629,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) if (adreno_is_a660(adreno_dev)) { if (adreno_is_a660(adreno_dev)) { kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1); kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1); kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); kgsl_regwrite(device, A6XX_UCHE_CMDQ_CONFIG, 0x90); } } if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV)) if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV)) Loading