Commit 24468374 authored Jan 14, 2016 by Nathan Sullivan Committed by David S. Miller Jan 15, 2016

net: macb: clear interrupts when disabling them



Disabling interrupts with the IDR register does not stop the macb hardware
from asserting its interrupt line if there are interrupts pending.  Always
clear the interrupts using ISR, and be sure to write it on hardware that
is not read-to-clear, like Zynq.  Not doing so will cause interrupts when
the driver doesn't expect them.

Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 65a5124a

drivers/net/ethernet/cadence/macb.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -1040,6 +1040,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
		/* close possible race with dev_close */
		if (unlikely(!netif_running(dev))) {
		queue_writel(queue, IDR, -1);
		if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
		queue_writel(queue, ISR, -1);
		break;
		}

		@@ -1561,6 +1563,8 @@ static void macb_reset_hw(struct macb *bp)
		for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
		queue_writel(queue, IDR, -1);
		queue_readl(queue, ISR);
		if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
		queue_writel(queue, ISR, -1);
		}
		}