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Commit 243c4b78 authored by Sean Paul's avatar Sean Paul
Browse files

Merge drm-misc-next-fixes-2019-05-20 into drm-misc-fixes 



Picking up 3 sun4i patches that missed the last drm-misc-next-fixes pull
request for 5.2

Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
parents a188339c 51a0d1a9

drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c

+3 −2
Original line number Diff line number Diff line
@@ -457,8 +457,9 @@ static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi, 
	u16 delay = 50 - 1;



	if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {

		delay = (mode->htotal - mode->hdisplay) * 150;

		delay /= (mode->clock / 1000) * 8;

		u32 hsync_porch = (mode->htotal - mode->hdisplay) * 150;



		delay = (hsync_porch / ((mode->clock / 1000) * 8));

		delay -= 50;

	}

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

+16 −13
Original line number Diff line number Diff line
@@ -293,7 +293,8 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi, 
				 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |

				 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);

		ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |

				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13);

				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |

				 SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);

	}



	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
@@ -672,22 +673,13 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 
				goto err_put_clk_pll0;

			}

		}



		ret = sun8i_phy_clk_create(phy, dev,

					   phy->variant->has_second_pll);

		if (ret) {

			dev_err(dev, "Couldn't create the PHY clock\n");

			goto err_put_clk_pll1;

		}



		clk_prepare_enable(phy->clk_phy);

	}



	phy->rst_phy = of_reset_control_get_shared(node, "phy");

	if (IS_ERR(phy->rst_phy)) {

		dev_err(dev, "Could not get phy reset control\n");

		ret = PTR_ERR(phy->rst_phy);

		goto err_disable_clk_phy;

		goto err_put_clk_pll1;

	}



	ret = reset_control_deassert(phy->rst_phy);
@@ -708,18 +700,29 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 
		goto err_disable_clk_bus;

	}



	if (phy->variant->has_phy_clk) {

		ret = sun8i_phy_clk_create(phy, dev,

					   phy->variant->has_second_pll);

		if (ret) {

			dev_err(dev, "Couldn't create the PHY clock\n");

			goto err_disable_clk_mod;

		}



		clk_prepare_enable(phy->clk_phy);

	}



	hdmi->phy = phy;



	return 0;



err_disable_clk_mod:

	clk_disable_unprepare(phy->clk_mod);

err_disable_clk_bus:

	clk_disable_unprepare(phy->clk_bus);

err_deassert_rst_phy:

	reset_control_assert(phy->rst_phy);

err_put_rst_phy:

	reset_control_put(phy->rst_phy);

err_disable_clk_phy:

	clk_disable_unprepare(phy->clk_phy);

err_put_clk_pll1:

	clk_put(phy->clk_pll1);

err_put_clk_pll0: