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Commit 23e7a718 authored by Dmitry Bogdanov's avatar Dmitry Bogdanov Committed by David S. Miller
Browse files

net: aquantia: add rx-flow filter definitions 



Add missing register definitions and the functions accessing them
related to rx-flow filters.

Signed-off-by: default avatarDmitry Bogdanov <dmitry.bogdanov@aquantia.com>
Signed-off-by: default avatarIgor Russkikh <igor.russkikh@aquantia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4fd3e2ac

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c

+109 −0
Original line number Original line Diff line number Diff line
@@ -898,6 +898,24 @@ void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, 
			    vlan_id_flr);

			    vlan_id_flr);

}

}





void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,

				    u32 filter)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter),

			    HW_ATL_RPF_VL_RXQ_EN_F_MSK,

			    HW_ATL_RPF_VL_RXQ_EN_F_SHIFT,

			    vlan_rxq_en);

}



void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,

				 u32 filter)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),

			    HW_ATL_RPF_VL_RXQ_F_MSK,

			    HW_ATL_RPF_VL_RXQ_F_SHIFT,

			    vlan_rxq);

};



void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,

void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,

				u32 filter)

				u32 filter)

{

{
@@ -965,6 +983,20 @@ void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter) 
			    HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);

			    HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);

}

}





void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter),

			    HW_ATL_RPF_L4_SPD_MSK,

			    HW_ATL_RPF_L4_SPD_SHIFT, val);

}



void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)

{

	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter),

			    HW_ATL_RPF_L4_DPD_MSK,

			    HW_ATL_RPF_L4_DPD_SHIFT, val);

}



/* RPO: rx packet offload */

/* RPO: rx packet offload */

void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,

void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,

					      u32 ipv4header_crc_offload_en)

					      u32 ipv4header_crc_offload_en)
@@ -1476,3 +1508,80 @@ void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr) 
			    HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,

			    HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,

			    up_force_intr);

			    up_force_intr);

}

}



void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)

{

	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U);

}



void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)

{

	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), 0U);

}



void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location)

{

	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), 0U);

}



void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)

{

	int i;



	for (i = 0; i < 4; ++i)

		aq_hw_write_reg(aq_hw,

				HW_ATL_RPF_L3_DSTA_ADR(location + i),

				0U);

}



void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)

{

	int i;



	for (i = 0; i < 4; ++i)

		aq_hw_write_reg(aq_hw,

				HW_ATL_RPF_L3_SRCA_ADR(location + i),

				0U);

}



void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,

				       u32 ipv4_dest)

{

	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location),

			ipv4_dest);

}



void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,

				      u32 ipv4_src)

{

	aq_hw_write_reg(aq_hw,

			HW_ATL_RPF_L3_SRCA_ADR(location),

			ipv4_src);

}



void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd)

{

	aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), cmd);

}



void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,

				      u32 *ipv6_src)

{

	int i;



	for (i = 0; i < 4; ++i)

		aq_hw_write_reg(aq_hw,

				HW_ATL_RPF_L3_SRCA_ADR(location + i),

				ipv6_src[i]);

}



void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,

				       u32 *ipv6_dest)

{

	int i;



	for (i = 0; i < 4; ++i)

		aq_hw_write_reg(aq_hw,

				HW_ATL_RPF_L3_DSTA_ADR(location + i),

				ipv6_dest[i]);

}

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h

+48 −0
Original line number Original line Diff line number Diff line
@@ -441,6 +441,14 @@ void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act, 
void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,

void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,

				u32 filter);

				u32 filter);





/* Set VLAN RX queue assignment enable */

void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,

				    u32 filter);



/* Set VLAN RX queue */

void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,

				 u32 filter);



/* set ethertype filter enable */

/* set ethertype filter enable */

void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,

void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,

				u32 filter);

				u32 filter);
@@ -475,6 +483,12 @@ void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, 
/* set ethertype filter */

/* set ethertype filter */

void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);

void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);





/* set L4 source port */

void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter);



/* set L4 destination port */

void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter);



/* rpo */

/* rpo */





/* set ipv4 header checksum offload enable */

/* set ipv4 header checksum offload enable */
@@ -704,4 +718,38 @@ void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis); 
/* set uP Force Interrupt */

/* set uP Force Interrupt */

void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr);

void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr);





/* clear ipv4 filter destination address */

void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location);



/* clear ipv4 filter source address */

void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location);



/* clear command for filter l3-l4 */

void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location);



/* clear ipv6 filter destination address */

void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location);



/* clear ipv6 filter source address */

void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location);



/* set ipv4 filter destination address */

void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,

				       u32 ipv4_dest);



/* set ipv4 filter source address */

void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,

				      u32 ipv4_src);



/* set command for filter l3-l4 */

void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd);



/* set ipv6 filter source address */

void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,

				      u32 *ipv6_src);



/* set ipv6 filter destination address */

void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,

				       u32 *ipv6_dest);



#endif /* HW_ATL_LLH_H */
 
#endif /* HW_ATL_LLH_H */

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h

+118 −17
Original line number Original line Diff line number Diff line
@@ -1092,24 +1092,43 @@ 
/* Default value of bitfield vl_id{F}[B:0] */

/* Default value of bitfield vl_id{F}[B:0] */

#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0

#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0





/* RX et_en{F} Bitfield Definitions

/* RX vl_rxq_en{F} Bitfield Definitions

 * Preprocessor definitions for the bitfield "et_en{F}".

 * Preprocessor definitions for the bitfield "vl_rxq{F}".

 * Parameter: filter {F} | stride size 0x4 | range [0, 15]

 * Parameter: filter {F} | stride size 0x4 | range [0, 15]

 * PORT="pif_rpf_et_en_i[0]"

 * PORT="pif_rpf_vl_rxq_en_i"

 */

 */





/* Register address for bitfield et_en{F} */

/* Register address for bitfield vl_rxq_en{F} */

#define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4)

#define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)

/* Bitmask for bitfield et_en{F} */

/* Bitmask for bitfield vl_rxq_en{F} */

#define HW_ATL_RPF_ET_EN_F_MSK 0x80000000

#define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000

/* Inverted bitmask for bitfield et_en{F} */

/* Inverted bitmask for bitfield vl_rxq_en{F}[ */

#define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF

#define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF

/* Lower bit position of bitfield et_en{F} */

/* Lower bit position of bitfield vl_rxq_en{F} */

#define HW_ATL_RPF_ET_EN_F_SHIFT 31

#define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28

/* Width of bitfield et_en{F} */

/* Width of bitfield vl_rxq_en{F} */

#define HW_ATL_RPF_ET_EN_F_WIDTH 1

#define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1

/* Default value of bitfield et_en{F} */

/* Default value of bitfield vl_rxq_en{F} */

#define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0

#define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0



/* RX vl_rxq{F}[4:0] Bitfield Definitions

 * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]".

 * Parameter: filter {F} | stride size 0x4 | range [0, 15]

 * PORT="pif_rpf_vl_rxq0_i[4:0]"

 */



/* Register address for bitfield vl_rxq{F}[4:0] */

#define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4)

/* Bitmask for bitfield vl_rxq{F}[4:0] */

#define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000

/* Inverted bitmask for bitfield vl_rxq{F}[4:0] */

#define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF

/* Lower bit position of bitfield vl_rxq{F}[4:0] */

#define HW_ATL_RPF_VL_RXQ_F_SHIFT 20

/* Width of bitfield vl_rxw{F}[4:0] */

#define HW_ATL_RPF_VL_RXQ_F_WIDTH 5

/* Default value of bitfield vl_rxq{F}[4:0] */

#define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0





/* rx et_en{f} bitfield definitions

/* rx et_en{f} bitfield definitions

 * preprocessor definitions for the bitfield "et_en{f}".

 * preprocessor definitions for the bitfield "et_en{f}".
@@ -1263,6 +1282,44 @@ 
/* default value of bitfield et_val{f}[f:0] */

/* default value of bitfield et_val{f}[f:0] */

#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0

#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0





/* RX l4_sp{D}[F:0] Bitfield Definitions

 * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]".

 * Parameter: srcport {D} | stride size 0x4 | range [0, 7]

 * PORT="pif_rpf_l4_sp0_i[15:0]"

 */



/* Register address for bitfield l4_sp{D}[F:0] */

#define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4)

/* Bitmask for bitfield l4_sp{D}[F:0] */

#define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu

/* Inverted bitmask for bitfield l4_sp{D}[F:0] */

#define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u

/* Lower bit position of bitfield l4_sp{D}[F:0] */

#define HW_ATL_RPF_L4_SPD_SHIFT 0

/* Width of bitfield l4_sp{D}[F:0] */

#define HW_ATL_RPF_L4_SPD_WIDTH 16

/* Default value of bitfield l4_sp{D}[F:0] */

#define HW_ATL_RPF_L4_SPD_DEFAULT 0x0



/* RX l4_dp{D}[F:0] Bitfield Definitions

 * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]".

 * Parameter: destport {D} | stride size 0x4 | range [0, 7]

 * PORT="pif_rpf_l4_dp0_i[15:0]"

 */



/* Register address for bitfield l4_dp{D}[F:0] */

#define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4)

/* Bitmask for bitfield l4_dp{D}[F:0] */

#define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu

/* Inverted bitmask for bitfield l4_dp{D}[F:0] */

#define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u

/* Lower bit position of bitfield l4_dp{D}[F:0] */

#define HW_ATL_RPF_L4_DPD_SHIFT 0

/* Width of bitfield l4_dp{D}[F:0] */

#define HW_ATL_RPF_L4_DPD_WIDTH 16

/* Default value of bitfield l4_dp{D}[F:0] */

#define HW_ATL_RPF_L4_DPD_DEFAULT 0x0



/* rx ipv4_chk_en bitfield definitions

/* rx ipv4_chk_en bitfield definitions

 * preprocessor definitions for the bitfield "ipv4_chk_en".

 * preprocessor definitions for the bitfield "ipv4_chk_en".

 * port="pif_rpo_ipv4_chk_en_i"

 * port="pif_rpo_ipv4_chk_en_i"
@@ -2418,4 +2475,48 @@ 
/* default value of bitfield uP Force Interrupt */

/* default value of bitfield uP Force Interrupt */

#define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0

#define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0





#define HW_ATL_RX_CTRL_ADDR_BEGIN_FL3L4   0x00005380

#define HW_ATL_RX_SRCA_ADDR_BEGIN_FL3L4   0x000053B0

#define HW_ATL_RX_DESTA_ADDR_BEGIN_FL3L4  0x000053D0



#define HW_ATL_RPF_L3_REG_CTRL_ADR(location) (0x00005380 + (location) * 0x4)



/* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions

 * Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]".

 * Parameter: location {D} | stride size 0x4 | range [0, 7]

 * PORT="pif_rpf_l3_sa0_i[31:0]"

 */



/* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */

#define HW_ATL_RPF_L3_SRCA_ADR(location) (0x000053B0 + (location) * 0x4)

/* Bitmask for bitfield l3_sa0[1F:0] */

#define HW_ATL_RPF_L3_SRCA_MSK 0xFFFFFFFFu

/* Inverted bitmask for bitfield l3_sa0[1F:0] */

#define HW_ATL_RPF_L3_SRCA_MSKN 0xFFFFFFFFu

/* Lower bit position of bitfield l3_sa0[1F:0] */

#define HW_ATL_RPF_L3_SRCA_SHIFT 0

/* Width of bitfield l3_sa0[1F:0] */

#define HW_ATL_RPF_L3_SRCA_WIDTH 32

/* Default value of bitfield l3_sa0[1F:0] */

#define HW_ATL_RPF_L3_SRCA_DEFAULT 0x0



/* RX rpf_l3_da{D}[1F:0] Bitfield Definitions

 * Preprocessor definitions for the bitfield "l3_da{D}[1F:0]".

 * Parameter: location {D} | stride size 0x4 | range [0, 7]

 * PORT="pif_rpf_l3_da0_i[31:0]"

 */



 /* Register address for bitfield pif_rpf_l3_da0_i[31:0] */

#define HW_ATL_RPF_L3_DSTA_ADR(location) (0x000053B0 + (location) * 0x4)

/* Bitmask for bitfield l3_da0[1F:0] */

#define HW_ATL_RPF_L3_DSTA_MSK 0xFFFFFFFFu

/* Inverted bitmask for bitfield l3_da0[1F:0] */

#define HW_ATL_RPF_L3_DSTA_MSKN 0xFFFFFFFFu

/* Lower bit position of bitfield l3_da0[1F:0] */

#define HW_ATL_RPF_L3_DSTA_SHIFT 0

/* Width of bitfield l3_da0[1F:0] */

#define HW_ATL_RPF_L3_DSTA_WIDTH 32

/* Default value of bitfield l3_da0[1F:0] */

#define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0



#endif /* HW_ATL_LLH_INTERNAL_H */
 
#endif /* HW_ATL_LLH_INTERNAL_H */