Loading drivers/net/bnx2.c +37 −24 Original line number Diff line number Diff line Loading @@ -3247,6 +3247,17 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) * before we issue a reset. */ val = REG_RD(bp, BNX2_MISC_ID); if (CHIP_NUM(bp) == CHIP_NUM_5709) { REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); REG_RD(bp, BNX2_MISC_COMMAND); udelay(5); val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val); } else { val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; Loading @@ -3255,16 +3266,17 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || (CHIP_ID(bp) == CHIP_ID_5706_A1)) msleep(15); (CHIP_ID(bp) == CHIP_ID_5706_A1)) { current->state = TASK_UNINTERRUPTIBLE; schedule_timeout(HZ / 50); } /* Reset takes approximate 30 usec */ for (i = 0; i < 10; i++) { val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) break; } udelay(10); } Loading @@ -3273,6 +3285,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) printk(KERN_ERR PFX "Chip reset did not complete\n"); return -EBUSY; } } /* Make sure byte swapping is properly configured. */ val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); Loading Loading @@ -3976,8 +3989,8 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) bp->tx_prod = NEXT_TX_BD(bp->tx_prod); bp->tx_prod_bseq += pkt_size; REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod); REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod); REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); udelay(100); Loading Loading @@ -4529,8 +4542,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) prod = NEXT_TX_BD(prod); bp->tx_prod_bseq += skb->len; REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); REG_WR16(bp, bp->tx_bidx_addr, prod); REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); mmiowb(); Loading Loading
drivers/net/bnx2.c +37 −24 Original line number Diff line number Diff line Loading @@ -3247,6 +3247,17 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) * before we issue a reset. */ val = REG_RD(bp, BNX2_MISC_ID); if (CHIP_NUM(bp) == CHIP_NUM_5709) { REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); REG_RD(bp, BNX2_MISC_COMMAND); udelay(5); val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val); } else { val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; Loading @@ -3255,16 +3266,17 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || (CHIP_ID(bp) == CHIP_ID_5706_A1)) msleep(15); (CHIP_ID(bp) == CHIP_ID_5706_A1)) { current->state = TASK_UNINTERRUPTIBLE; schedule_timeout(HZ / 50); } /* Reset takes approximate 30 usec */ for (i = 0; i < 10; i++) { val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) break; } udelay(10); } Loading @@ -3273,6 +3285,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) printk(KERN_ERR PFX "Chip reset did not complete\n"); return -EBUSY; } } /* Make sure byte swapping is properly configured. */ val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); Loading Loading @@ -3976,8 +3989,8 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) bp->tx_prod = NEXT_TX_BD(bp->tx_prod); bp->tx_prod_bseq += pkt_size; REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod); REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod); REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); udelay(100); Loading Loading @@ -4529,8 +4542,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) prod = NEXT_TX_BD(prod); bp->tx_prod_bseq += skb->len; REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); REG_WR16(bp, bp->tx_bidx_addr, prod); REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq); mmiowb(); Loading