Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 233fa44b authored by Jiri Pirko's avatar Jiri Pirko Committed by David S. Miller
Browse files

mlxsw: pci: Implement reset done check 



Firmware now tells us that the reset is done by passing a magic value
via register. Use it to shorten the wait in case this is supported.
With old firmware, we still wait until the timeout is reached.

Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent cea8768f

drivers/net/ethernet/mellanox/mlxsw/pci.c

+11 −4
Original line number Diff line number Diff line
@@ -1681,11 +1681,18 @@ static const struct mlxsw_bus mlxsw_pci_bus = { 


static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci)

{

	unsigned long end;



	mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT);

	/* Current firware does not let us know when the reset is done.

	 * So we just wait here for constant time and hope for the best.

	 */

	msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);

	wmb(); /* reset needs to be written before we read control register */

	end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);

	do {

		u32 val = mlxsw_pci_read32(mlxsw_pci, FW_READY);



		if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)

			break;

		cond_resched();

	} while (time_before(jiffies, end));

	return 0;

}

drivers/net/ethernet/mellanox/mlxsw/pci.h

+3 −0
Original line number Diff line number Diff line
@@ -61,6 +61,9 @@ 
#define MLXSW_PCI_SW_RESET			0xF0010

#define MLXSW_PCI_SW_RESET_RST_BIT		BIT(0)

#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS	5000

#define MLXSW_PCI_FW_READY			0xA1844

#define MLXSW_PCI_FW_READY_MASK			0xFF

#define MLXSW_PCI_FW_READY_MAGIC		0x5E



#define MLXSW_PCI_DOORBELL_SDQ_OFFSET		0x000

#define MLXSW_PCI_DOORBELL_RDQ_OFFSET		0x200