Loading arch/x86/kvm/emulate.c +1 −1 Original line number Diff line number Diff line Loading @@ -3603,7 +3603,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) break; case Src2CL: ctxt->src2.bytes = 1; ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0x8; ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0xff; break; case Src2ImmByte: rc = decode_imm(ctxt, &ctxt->src2, 1, true); Loading arch/x86/kvm/mmu.c +2 −1 Original line number Diff line number Diff line Loading @@ -400,7 +400,8 @@ static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) /* xchg acts as a barrier before the setting of the high bits */ orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); orig.spte_high = ssptep->spte_high = sspte.spte_high; orig.spte_high = ssptep->spte_high; ssptep->spte_high = sspte.spte_high; count_spte_clear(sptep, spte); return orig.spte; Loading Loading
arch/x86/kvm/emulate.c +1 −1 Original line number Diff line number Diff line Loading @@ -3603,7 +3603,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) break; case Src2CL: ctxt->src2.bytes = 1; ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0x8; ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0xff; break; case Src2ImmByte: rc = decode_imm(ctxt, &ctxt->src2, 1, true); Loading
arch/x86/kvm/mmu.c +2 −1 Original line number Diff line number Diff line Loading @@ -400,7 +400,8 @@ static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) /* xchg acts as a barrier before the setting of the high bits */ orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); orig.spte_high = ssptep->spte_high = sspte.spte_high; orig.spte_high = ssptep->spte_high; ssptep->spte_high = sspte.spte_high; count_spte_clear(sptep, spte); return orig.spte; Loading