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Commit 231d8908 authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Simon Horman
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arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices 



This patch defines OOP tables for all CPUs, similarly to
what done by Takeshi Kihara and Yoshihiro Kaneko for the
R8A77990.

Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent dd7188eb

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -44,6 +44,27 @@ 
		clock-frequency = <0>;

	};



	cluster1_opp: opp_table10 {

		compatible = "operating-points-v2";

		opp-shared;

		opp-800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

			opp-suspend;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -55,6 +76,8 @@ 
			power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_1: cpu@1 {
@@ -64,6 +87,8 @@ 
			power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		L2_CA53: cache-controller-0 {