Merge "dt-bindings: interconnect: add interconnect bindings"

Required properties :

- compatible : shall contain only one of the following:

			"qcom,lahaina-epss-l3-shared",

			"qcom,lahaina-epss-l3-cpu";

			"qcom,lahaina-epss-l3-cpu",

			"qcom,shima-epss-l3-cpu",

			"qcom,shima-epss-l3-shared";

- reg : Address and length of the register set for the device

- clock-names: should contain "xo", "alternate"

- clocks: list of phandle and clock specifier pairs corresponding to

Qualcomm Technologies, Inc. Shima Network-On-Chip interconnect driver binding

-----------------------------------------------------------

Shima interconnect providers support system bandwidth requirements through

RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is

able to communicate with the BCM through the Resource State Coordinator (RSC)

associated with each execution environment. Provider nodes must point to at

least one RPMh device child node pertaining to their RSC and each provider

can map to multiple RPMh resources.

Required properties :

- compatible : shall contain only one of the following:

			"qcom,shima-aggre1_noc",

			"qcom,shima-aggre2_noc",

			"qcom,shima-clk_virt",

			"qcom,shima-config_noc",

			"qcom,shima-dc_noc",

			"qcom,shima-gem_noc",

			"qcom,shima-lpass_ag_noc",

			"qcom,shima-mc_virt",

			"qcom,shima-mmss_noc",

			"qcom,shima-nsp_noc",

			"qcom,shima-system_noc",

- #interconnect-cells : should contain 1

Examples:

aggre1_noc: interconnect@16e0000 {

	compatible = "qcom,shima-aggre1_noc";

	interconnect-cells = <1>;

};