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Commit 22c58fd7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC platform updates from Olof Johansson:
 "SoC updates, mostly refactorings and cleanups of old legacy platforms.

  Major themes this release:

   - Conversion of ixp4xx to a modern platform (drivers, DT, bindings)

   - Moving some of the ep93xx headers around to get it closer to
     multiplatform enabled.

   - Cleanups of Davinci

  This also contains a few patches that were queued up as fixes before
  5.1 but I didn't get sent in before release"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (123 commits)
  ARM: debug-ll: add default address for digicolor
  ARM: u300: regulator: add MODULE_LICENSE()
  ARM: ep93xx: move private headers out of mach/*
  ARM: ep93xx: move pinctrl interfaces into include/linux/soc
  ARM: ep93xx: keypad: stop using mach/platform.h
  ARM: ep93xx: move network platform data to separate header
  ARM: stm32: add AMBA support for stm32 family
  MAINTAINERS: update arch/arm/mach-davinci
  ARM: rockchip: add missing of_node_put in rockchip_smp_prepare_pmu
  ARM: dts: Add queue manager and NPE to the IXP4xx DTSI
  soc: ixp4xx: qmgr: Add DT probe code
  soc: ixp4xx: qmgr: Add DT bindings for IXP4xx qmgr
  soc: ixp4xx: npe: Add DT probe code
  soc: ixp4xx: Add DT bindings for IXP4xx NPE
  soc: ixp4xx: qmgr: Pass resources
  soc: ixp4xx: Remove unused functions
  soc: ixp4xx: Uninline several functions
  soc: ixp4xx: npe: Pass addresses as resources
  ARM: ixp4xx: Turn the QMGR into a platform device
  ARM: ixp4xx: Turn the NPE into a platform device
  ...
parents a455eda3 7a0c4c17

Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel IXP4xx Device Tree Bindings



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - linksys,nslu2

          - const: intel,ixp42x

      - items:

          - enum:

              - gateworks,gw2358

          - const: intel,ixp43x

Documentation/devicetree/bindings/bus/ti-sysc.txt

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Original line number Diff line number Diff line
@@ -94,6 +94,8 @@ Optional properties: 


- ti,no-idle-on-init	interconnect target module should not be idled at init



- ti,no-idle		interconnect target module should not be idled



Example: Single instance of MUSB controller on omap4 using interconnect ranges

using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
@@ -131,6 +133,6 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): 
		};

	};



Note that other SoCs, such as am335x can have multipe child devices. On am335x

Note that other SoCs, such as am335x can have multiple child devices. On am335x

there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA

instance as children of a single interconnet target module.
 
instance as children of a single interconnect target module.

Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2019 Linaro Ltd.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel IXP4xx Network Processing Engine



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



description: |

  On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small

  processor that can load a firmware to perform offloading of networking

  and crypto tasks. It also manages the MDIO bus to the ethernet PHYs

  on the IXP4xx platform. All IXP4xx platforms have three NPEs at

  consecutive memory locations. They are all included in the same

  device node since they are not independent of each other.



properties:

  compatible:

    oneOf:

      - items:

          - const: intel,ixp4xx-network-processing-engine



  reg:

    minItems: 3

    maxItems: 3

    items:

      - description: NPE0 register range

      - description: NPE1 register range

      - description: NPE2 register range



required:

  - compatible

  - reg



examples:

  - |

    npe@c8006000 {

         compatible = "intel,ixp4xx-network-processing-engine";

         reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;

    };

Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2018 Linaro Ltd.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/interrupt/intel-ixp4xx-interrupt.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel IXP4xx XScale Networking Processors Interrupt Controller



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



description: |

  This interrupt controller is found in the Intel IXP4xx processors.

  Some processors have 32 interrupts, some have up to 64 interrupts.

  The exact number of interrupts is determined from the compatible

  string.



  The distinct IXP4xx families with different interrupt controller

  variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four

  families were the only ones to reach the developer and consumer

  market.



properties:

  compatible:

    items:

      - enum:

        - intel,ixp42x-interrupt

        - intel,ixp43x-interrupt

        - intel,ixp45x-interrupt

        - intel,ixp46x-interrupt



  reg:

    maxItems: 1



  interrupt-controller: true



  '#interrupt-cells':

    const: 2



required:

  - compatible

  - reg

  - interrupt-controller

  - '#interrupt-cells'



examples:

  - |

    intcon: interrupt-controller@c8003000 {

        compatible = "intel,ixp43x-interrupt";

        reg = <0xc8003000 0x100>;

        interrupt-controller;

        #interrupt-cells = <2>;

    };

Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2019 Linaro Ltd.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/misc/intel-ixp4xx-ahb-queue-manager.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel IXP4xx AHB Queue Manager



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



description: |

  The IXP4xx AHB Queue Manager maintains queues as circular buffers in

  an 8KB embedded SRAM along with hardware pointers. It is used by both

  the XScale processor and the NPEs (Network Processing Units) in the

  IXP4xx for accelerating queues, especially for networking. Clients pick

  queues from the queue manager with foo-queue = <&qmgr N> where the

  &qmgr is a phandle to the queue manager and N is the queue resource

  number. The queue resources available and their specific purpose

  on a certain IXP4xx system will vary.



properties:

  compatible:

    items:

      - const: intel,ixp4xx-ahb-queue-manager



  reg:

    maxItems: 1



  interrupts:

    items:

      - description: Interrupt for queues 0-31

      - description: Interrupt for queues 32-63



required:

  - compatible

  - reg

  - interrupts



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    qmgr: queue-manager@60000000 {

         compatible = "intel,ixp4xx-ahb-queue-manager";

         reg = <0x60000000 0x4000>;

         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;

    };