Merge "ARM: dts: msm: Add eMMC, SD card support for yupik" (22b6d32f) · Commits · e / devices / android_kernel_fairphone_FP5

qcom/yupik-pinctrl.dtsi

+102 −0

Original line number	Original line	Diff line number	Diff line
	@@ -37,6 +37,108 @@
	};		};
	};		};

			sdc1_on: sdc1_on {
			clk {
			pins = "sdc1_clk";
			bias-disable;
			drive-strength = <16>;
			};

			cmd {
			pins = "sdc1_cmd";
			bias-pull-up;
			drive-strength = <10>;
			};

			data {
			pins = "sdc1_data";
			bias-pull-up;
			drive-strength = <10>;
			};

			rclk {
			pins = "sdc1_rclk";
			bias-pull-down;
			};
			};

			sdc1_off: sdc1_off {
			clk {
			pins = "sdc1_clk";
			bias-disable;
			drive-strength = <2>;
			};

			cmd {
			pins = "sdc1_cmd";
			bias-pull-up;
			drive-strength = <2>;
			};

			data {
			pins = "sdc1_data";
			bias-pull-up;
			drive-strength = <2>;
			};

			rclk {
			pins = "sdc1_rclk";
			bias-pull-down;
			};
			};

			sdc2_on: sdc2_on {
			clk {
			pins = "sdc2_clk";
			bias-disable;
			drive-strength = <16>;
			};

			cmd {
			pins = "sdc2_cmd";
			bias-pull-up;
			drive-strength = <10>;
			};

			data {
			pins = "sdc2_data";
			bias-pull-up;
			drive-strength = <10>;
			};

			sd-cd {
			pins = "gpio91";
			bias-pull-up;
			drive-strength = <2>;
			};
			};

			sdc2_off: sdc2_off {
			clk {
			pins = "sdc2_clk";
			bias-disable;
			drive-strength = <2>;
			};

			cmd {
			pins = "sdc2_cmd";
			bias-pull-up;
			drive-strength = <2>;
			};

			data {
			pins = "sdc2_data";
			bias-pull-up;
			drive-strength = <2>;
			};

			sd-cd {
			pins = "gpio91";
			bias-disable;
			drive-strength = <2>;
			};
			};

	qupv3_se0_spi_pins: qupv3_se0_spi_pins {		qupv3_se0_spi_pins: qupv3_se0_spi_pins {
	qupv3_se0_spi_active: qupv3_se0_spi_active {		qupv3_se0_spi_active: qupv3_se0_spi_active {
	mux {		mux {

qcom/yupik-rumi.dtsi

+41 −1

Original line number	Original line	Diff line number	Diff line
	#include <dt-bindings/clock/qcom,gcc-yupik.h>		#include <dt-bindings/clock/qcom,gcc-yupik.h>
			#include <dt-bindings/gpio/gpio.h>
	&soc {		&soc {
	timer {		timer {
	clock-frequency = <5000000>;		clock-frequency = <5000000>;
	@@ -54,6 +54,46 @@
	};		};
	};		};

			&sdhc_1 {
			status = "disabled";

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&sdc1_on>;
			pinctrl-1 = <&sdc1_off>;

			vdd-supply = <&L7B>;
			qcom,vdd-voltage-level = <2960000 2960000>;
			qcom,vdd-current-level = <0 570000>;

			vdd-io-supply = <&L19B>;
			qcom,vdd-io-always-on;
			qcom,vdd-io-lpm-sup;
			qcom,vdd-io-voltage-level = <1800000 1800000>;
			qcom,vdd-io-current-level = <0 325000>;

			cap-mmc-highspeed;
			};

			&sdhc_2 {
			status = "disabled";

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&sdc2_on>;
			pinctrl-1 = <&sdc2_off>;

			vdd-supply = <&L9C>;
			qcom,vdd-voltage-level = <2960000 2960000>;
			qcom,vdd-current-level = <0 800000>;

			vdd-io-supply = <&L6C>;
			qcom,vdd-io-voltage-level = <1800000 2960000>;
			qcom,vdd-io-current-level = <0 22000>;

			cap-sd-highspeed;

			cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
			};

	&ufsphy_mem {		&ufsphy_mem {
	compatible = "qcom,ufs-phy-qrbtc-sdm845";		compatible = "qcom,ufs-phy-qrbtc-sdm845";

qcom/yupik.dtsi

+77 −0

Original line number	Original line	Diff line number	Diff line
	@@ -26,6 +26,8 @@

	aliases {		aliases {
	ufshc1 = &ufshc_mem; /* Embedded UFS Slot */		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
			sdhc0 = &sdhc_1; /SDC1 eMMC slot/
			sdhc1 = &sdhc_2; /* SDC2 SD card slot */
	};		};

	firmware: firmware {		firmware: firmware {
	@@ -1229,6 +1231,81 @@
	interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
	};		};

			sdhc_1: sdhci@7C4000 {
			compatible = "qcom,sdhci-msm-v5";
			reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>;
			reg-names = "hc_mem", "cqhci_mem";

			interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
			<&gcc GCC_SDCC1_AHB_CLK>,
			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
			clock-names = "core", "iface", "ice_core";

			qcom,ice-clk-rates = <300000000 100000000>;

			/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
			qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>;

			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			mmc-hs400-1_8v;
			mmc-hs400-enhanced-strobe;

			bus-width = <8>;
			non-removable;
			supports-cqe;

			qcom,devfreq,freq-table = <50000000 200000000>;
			qcom,scaling-lower-bus-speed-mode = "DDR52";

			status = "disabled";

			qos0 {
			mask = <0x0f>;
			vote = <61>;
			};

			qos1 {
			mask = <0xf0>;
			vote = <67>;
			};
			};

			sdhc_2: sdhci@8804000 {
			compatible = "qcom,sdhci-msm-v5";
			reg = <0x08804000 0x1000>;
			reg-names = "hc_mem";

			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";

			bus-width = <4>;
			/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
			qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;

			qcom,devfreq,freq-table = <50000000 202000000>;

			status = "disabled";

			qos0 {
			mask = <0x0f>;
			vote = <61>;
			};

			qos1 {
			mask = <0xf0>;
			vote = <67>;
			};
			};

	qcom,lpass@3700000 {		qcom,lpass@3700000 {
	compatible = "qcom,pil-tz-generic";		compatible = "qcom,pil-tz-generic";
	reg = <0x3700000 0x00100>;		reg = <0x3700000 0x00100>;