Merge "UPSTREAM: mmc: sdhci-msm: Add CQHCI support for sdhci-msm" (2273336b) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/mmc/host/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -489,6 +489,7 @@ config MMC_SDHCI_MSM
		depends on ARCH_QCOM \|\| (ARM && COMPILE_TEST)
		depends on MMC_SDHCI_PLTFM
		select MMC_SDHCI_IO_ACCESSORS
		select MMC_CQHCI
		help
		This selects the Secure Digital Host Controller Interface (SDHCI)
		support present in Qualcomm SOCs. The controller supports

drivers/mmc/host/sdhci-msm.c

+158 −1

Original line number	Diff line number	Diff line
		@@ -16,6 +16,7 @@
		#include <linux/regulator/consumer.h>

		#include "sdhci-pltfm.h"
		#include "cqhci.h"

		#define CORE_MCI_VERSION 0x50
		#define CORE_VERSION_MAJOR_SHIFT 28
		@@ -135,6 +136,10 @@
		#define msm_host_writel(msm_host, val, host, offset) \
		msm_host->var_ops->msm_writel_relaxed(val, host, offset)

		/* CQHCI vendor specific registers */
		#define CQHCI_VENDOR_CFG1 0xA00
		#define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)

		struct sdhci_msm_offset {
		u32 core_hc_mode;
		u32 core_mci_data_cnt;
		@@ -2860,6 +2865,153 @@ static void sdhci_msm_bus_voting(struct sdhci_host *host, bool enable)
		sdhci_msm_bus_queue_work(host);
		}

		/*****************************************************************************\
		* *
		* MSM Command Queue Engine (CQE) *
		* *
		\*****************************************************************************/

		static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
		{
		int cmd_error = 0;
		int data_error = 0;

		if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
		return intmask;

		cqhci_irq(host->mmc, intmask, cmd_error, data_error);
		return 0;
		}

		static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
		{
		struct sdhci_host *host = mmc_priv(mmc);
		unsigned long flags;
		u32 ctrl;

		/*
		* When CQE is halted, the legacy SDHCI path operates only
		* on 16-byte descriptors in 64bit mode.
		*/
		if (host->flags & SDHCI_USE_64_BIT_DMA)
		host->desc_sz = 16;

		spin_lock_irqsave(&host->lock, flags);

		/*
		* During CQE command transfers, command complete bit gets latched.
		* So s/w should clear command complete interrupt status when CQE is
		* either halted or disabled. Otherwise unexpected SDCHI legacy
		* interrupt gets triggered when CQE is halted/disabled.
		*/
		ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
		ctrl \|= SDHCI_INT_RESPONSE;
		sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
		sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);

		spin_unlock_irqrestore(&host->lock, flags);

		sdhci_cqe_disable(mmc, recovery);
		}

		static void sdhci_msm_cqe_enable(struct mmc_host *mmc)
		{
		struct sdhci_host *host = mmc_priv(mmc);

		#if !defined(CONFIG_SDC_QTI)
		if (host->flags & SDHCI_USE_64_BIT_DMA)
		host->desc_sz = 12;
		#endif
		sdhci_cqe_enable(mmc);

		/* Set maximum timeout as per qti spec */
		sdhci_writeb(host, 0xF, SDHCI_TIMEOUT_CONTROL);
		}

		static void sdhci_msm_cqe_sdhci_dumpregs(struct mmc_host *mmc)
		{
		struct sdhci_host *host = mmc_priv(mmc);

		sdhci_dumpregs(host);
		}

		static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
		.enable = sdhci_msm_cqe_enable,
		.disable = sdhci_msm_cqe_disable,
		.dumpregs = sdhci_msm_cqe_sdhci_dumpregs,
		};

		static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
		struct platform_device *pdev)
		{
		struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
		struct cqhci_host *cq_host;
		bool dma64;
		u32 cqcfg;
		int ret;

		#if defined(CONFIG_SDC_QTI)
		/*
		* When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
		* So ensure ADMA table is allocated for 16byte descriptors.
		*/
		if (host->caps & SDHCI_CAN_64BIT)
		host->alloc_desc_sz = 16;
		#endif

		ret = sdhci_setup_host(host);
		if (ret)
		return ret;

		cq_host = cqhci_pltfm_init(pdev);
		if (IS_ERR(cq_host)) {
		ret = PTR_ERR(cq_host);
		dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
		goto cleanup;
		}

		msm_host->mmc->caps2 \|= MMC_CAP2_CQE \| MMC_CAP2_CQE_DCMD;
		cq_host->ops = &sdhci_msm_cqhci_ops;

		dma64 = host->flags & SDHCI_USE_64_BIT_DMA;

		ret = cqhci_init(cq_host, host->mmc, dma64);
		if (ret) {
		dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
		mmc_hostname(host->mmc), ret);
		goto cleanup;
		}

		/* Disable cqe reset due to cqe enable signal */
		cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
		cqcfg \|= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
		cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);

		#if defined(CONFIG_SDC_QTI)
		/*
		* SDHC expects 12byte ADMA descriptors till CQE is enabled.
		* So limit desc_sz to 12 so that the data commands that are sent
		* during card initialization (before CQE gets enabled) would
		* get executed without any issues.
		*/
		if (host->flags & SDHCI_USE_64_BIT_DMA)
		host->desc_sz = 12;
		#endif

		ret = __sdhci_add_host(host);
		if (ret)
		goto cleanup;

		dev_info(&pdev->dev, "%s: CQE init: success\n",
		mmc_hostname(host->mmc));
		return ret;

		cleanup:
		sdhci_cleanup_host(host);
		return ret;
		}

		static const struct sdhci_msm_variant_ops mci_var_ops = {
		.msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
		.msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
		@@ -2906,6 +3058,7 @@ static const struct sdhci_ops sdhci_msm_ops = {
		.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
		.write_w = sdhci_msm_writew,
		.write_b = sdhci_msm_writeb,
		.irq = sdhci_msm_cqe_irq,
		};

		static const struct sdhci_pltfm_data sdhci_msm_pdata = {
		@@ -3006,6 +3159,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
		const struct sdhci_msm_offset *msm_offset;
		const struct sdhci_msm_variant_info *var_info;
		struct device *dev = &pdev->dev;
		struct device_node *node = pdev->dev.of_node;

		host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
		if (IS_ERR(host))
		@@ -3237,6 +3391,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
		pm_runtime_use_autosuspend(&pdev->dev);

		host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
		if (of_property_read_bool(node, "supports-cqe"))
		ret = sdhci_msm_cqe_add_host(host, pdev);
		else
		ret = sdhci_add_host(host);
		if (ret)
		goto pm_runtime_disable;

drivers/mmc/host/sdhci.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -3811,6 +3811,15 @@ int sdhci_setup_host(struct sdhci_host *host)
		dma_addr_t dma;
		void *buf;

		#if defined(CONFIG_SDC_QTI)
		if (!(host->flags & SDHCI_USE_64_BIT_DMA))
		host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
		else if (!host->alloc_desc_sz)
		host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);

		host->desc_sz = host->alloc_desc_sz;
		host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
		#else
		if (host->flags & SDHCI_USE_64_BIT_DMA) {
		host->adma_table_sz = host->adma_table_cnt *
		SDHCI_ADMA2_64_DESC_SZ(host);
		@@ -3820,6 +3829,7 @@ int sdhci_setup_host(struct sdhci_host *host)
		SDHCI_ADMA2_32_DESC_SZ;
		host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
		}
		#endif

		host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
		/*

drivers/mmc/host/sdhci.h

+4 −1

Original line number	Diff line number	Diff line
		@@ -556,7 +556,10 @@ struct sdhci_host {
		dma_addr_t adma_addr; /* Mapped ADMA descr. table */
		dma_addr_t align_addr; /* Mapped bounce buffer */

		unsigned int desc_sz; /* ADMA descriptor size */
		unsigned int desc_sz; /* ADMA current descriptor size */
		#if defined(CONFIG_SDC_QTI)
		unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
		#endif

		struct workqueue_struct complete_wq; / Request completion wq */
		struct work_struct complete_work; /* Request completion work */