Loading drivers/pinctrl/qcom/pinctrl-lahaina.c +2 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,8 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ .egpio_enable = 12, \ .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ Loading drivers/pinctrl/qcom/pinctrl-msm.c +4 −0 Original line number Diff line number Diff line Loading @@ -180,6 +180,10 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, val = msm_readl_ctl(pctrl, g); val &= ~mask; val |= i << g->mux_bit; /* Check if egpio present and enable that feature */ if (val & BIT(g->egpio_present)) val |= BIT(g->egpio_enable); msm_writel_ctl(val, pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); Loading drivers/pinctrl/qcom/pinctrl-msm.h +2 −0 Original line number Diff line number Diff line Loading @@ -75,6 +75,8 @@ struct msm_pingroup { unsigned pull_bit:5; unsigned drv_bit:5; unsigned egpio_enable:5; unsigned egpio_present:5; unsigned oe_bit:5; unsigned in_bit:5; unsigned out_bit:5; Loading Loading
drivers/pinctrl/qcom/pinctrl-lahaina.c +2 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,8 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ .egpio_enable = 12, \ .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ Loading
drivers/pinctrl/qcom/pinctrl-msm.c +4 −0 Original line number Diff line number Diff line Loading @@ -180,6 +180,10 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, val = msm_readl_ctl(pctrl, g); val &= ~mask; val |= i << g->mux_bit; /* Check if egpio present and enable that feature */ if (val & BIT(g->egpio_present)) val |= BIT(g->egpio_enable); msm_writel_ctl(val, pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); Loading
drivers/pinctrl/qcom/pinctrl-msm.h +2 −0 Original line number Diff line number Diff line Loading @@ -75,6 +75,8 @@ struct msm_pingroup { unsigned pull_bit:5; unsigned drv_bit:5; unsigned egpio_enable:5; unsigned egpio_present:5; unsigned oe_bit:5; unsigned in_bit:5; unsigned out_bit:5; Loading