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Commit 223a6fdf authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: implement timing override workarounds on LPT 



These workarounds are documented on the CRT mode set sequence.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8a52fd9f

drivers/gpu/drm/i915/intel_display.c

+10 −0
Original line number Diff line number Diff line
@@ -1729,6 +1729,11 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 
	assert_fdi_tx_enabled(dev_priv, cpu_transcoder);

	assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);



	/* Workaround: set timing override bit. */

	val = I915_READ(_TRANSA_CHICKEN2);

	val |= TRANS_AUTOTRAIN_GEN_STALL_DIS;

	I915_WRITE(_TRANSA_CHICKEN2, val);



	val = TRANS_ENABLE;

	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
@@ -1780,6 +1785,11 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv, 
	/* wait for PCH transcoder off, transcoder state */

	if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))

		DRM_ERROR("Failed to disable PCH transcoder\n");



	/* Workaround: clear timing override bit. */

	val = I915_READ(_TRANSA_CHICKEN2);

	val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS;

	I915_WRITE(_TRANSA_CHICKEN2, val);

}



/**