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Commit 2239e6df authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
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drm/i915/guc: prefer intel_gt in guc interrupt functions 



We can get rid of a few more guc_to_i915 and start compartmentalizing
interrupt management a bit more. We should be able to move more code in
the future once the gt_pm code is also moved across to gt.

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190713100016.8026-10-chris@chris-wilson.co.uk


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 84b1ca2f

drivers/gpu/drm/i915/gt/intel_gt_types.h

+2 −0
Original line number Diff line number Diff line
@@ -74,6 +74,8 @@ struct intel_gt { 


	u32 pm_imr;

	u32 pm_ier;



	u32 pm_guc_events;

};



enum intel_gt_scratch_field {

drivers/gpu/drm/i915/i915_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -1400,7 +1400,6 @@ struct drm_i915_private { 
	};

	u32 gt_irq_mask;

	u32 pm_rps_events;

	u32 pm_guc_events;

	u32 pipestat_irq_mask[I915_MAX_PIPES];



	struct i915_hotplug hotplug;

drivers/gpu/drm/i915/i915_irq.c

+40 −33
Original line number Diff line number Diff line
@@ -42,6 +42,8 @@ 
#include "display/intel_lpe_audio.h"

#include "display/intel_psr.h"



#include "gt/intel_gt.h"



#include "i915_drv.h"

#include "i915_irq.h"

#include "i915_trace.h"
@@ -601,85 +603,90 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) 


void gen9_reset_guc_interrupts(struct intel_guc *guc)

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct intel_gt *gt = guc_to_gt(guc);

	struct drm_i915_private *i915 = gt->i915;



	assert_rpm_wakelock_held(&dev_priv->runtime_pm);

	assert_rpm_wakelock_held(&i915->runtime_pm);



	spin_lock_irq(&dev_priv->irq_lock);

	gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);

	spin_unlock_irq(&dev_priv->irq_lock);

	spin_lock_irq(&i915->irq_lock);

	gen6_reset_pm_iir(i915, gt->pm_guc_events);

	spin_unlock_irq(&i915->irq_lock);

}



void gen9_enable_guc_interrupts(struct intel_guc *guc)

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct intel_gt *gt = guc_to_gt(guc);

	struct drm_i915_private *i915 = gt->i915;



	assert_rpm_wakelock_held(&dev_priv->runtime_pm);

	assert_rpm_wakelock_held(&i915->runtime_pm);



	spin_lock_irq(&dev_priv->irq_lock);

	spin_lock_irq(&i915->irq_lock);

	if (!guc->interrupts.enabled) {

		WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &

				       dev_priv->pm_guc_events);

		WARN_ON_ONCE(intel_uncore_read(gt->uncore, gen6_pm_iir(i915)) &

			     gt->pm_guc_events);

		guc->interrupts.enabled = true;

		gen6_enable_pm_irq(&dev_priv->gt, dev_priv->pm_guc_events);

		gen6_enable_pm_irq(gt, gt->pm_guc_events);

	}

	spin_unlock_irq(&dev_priv->irq_lock);

	spin_unlock_irq(&i915->irq_lock);

}



void gen9_disable_guc_interrupts(struct intel_guc *guc)

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct intel_gt *gt = guc_to_gt(guc);

	struct drm_i915_private *i915 = gt->i915;



	assert_rpm_wakelock_held(&dev_priv->runtime_pm);

	assert_rpm_wakelock_held(&i915->runtime_pm);



	spin_lock_irq(&dev_priv->irq_lock);

	spin_lock_irq(&i915->irq_lock);

	guc->interrupts.enabled = false;



	gen6_disable_pm_irq(&dev_priv->gt, dev_priv->pm_guc_events);

	gen6_disable_pm_irq(gt, gt->pm_guc_events);



	spin_unlock_irq(&dev_priv->irq_lock);

	intel_synchronize_irq(dev_priv);

	spin_unlock_irq(&i915->irq_lock);

	intel_synchronize_irq(i915);



	gen9_reset_guc_interrupts(guc);

}



void gen11_reset_guc_interrupts(struct intel_guc *guc)

{

	struct drm_i915_private *i915 = guc_to_i915(guc);

	struct intel_gt *gt = guc_to_gt(guc);

	struct drm_i915_private *i915 = gt->i915;



	spin_lock_irq(&i915->irq_lock);

	gen11_reset_one_iir(&i915->gt, 0, GEN11_GUC);

	gen11_reset_one_iir(gt, 0, GEN11_GUC);

	spin_unlock_irq(&i915->irq_lock);

}



void gen11_enable_guc_interrupts(struct intel_guc *guc)

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct intel_gt *gt = guc_to_gt(guc);



	spin_lock_irq(&dev_priv->irq_lock);

	spin_lock_irq(&gt->i915->irq_lock);

	if (!guc->interrupts.enabled) {

		u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);



		WARN_ON_ONCE(gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GUC));

		I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);

		I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~events);

		WARN_ON_ONCE(gen11_reset_one_iir(gt, 0, GEN11_GUC));

		intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, events);

		intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~events);

		guc->interrupts.enabled = true;

	}

	spin_unlock_irq(&dev_priv->irq_lock);

	spin_unlock_irq(&gt->i915->irq_lock);

}



void gen11_disable_guc_interrupts(struct intel_guc *guc)

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct intel_gt *gt = guc_to_gt(guc);

	struct drm_i915_private *i915 = gt->i915;



	spin_lock_irq(&dev_priv->irq_lock);

	spin_lock_irq(&i915->irq_lock);

	guc->interrupts.enabled = false;



	I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);

	I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);

	intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);

	intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);



	spin_unlock_irq(&dev_priv->irq_lock);

	intel_synchronize_irq(dev_priv);

	spin_unlock_irq(&i915->irq_lock);

	intel_synchronize_irq(i915);



	gen11_reset_guc_interrupts(guc);

}
@@ -4757,7 +4764,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) 


	/* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */

	if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)

		dev_priv->pm_guc_events = GUC_INTR_GUC2HOST << 16;

		dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;



	/* Let's track the enabled rps events */

	if (IS_VALLEYVIEW(dev_priv))