qed*: HSI renaming for different types of HW (21dd79e8) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/infiniband/hw/qedr/main.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -264,7 +264,7 @@ static int qedr_register_device(struct qedr_dev *dev)
	static int qedr_alloc_mem_sb(struct qedr_dev *dev,		static int qedr_alloc_mem_sb(struct qedr_dev *dev,
	struct qed_sb_info *sb_info, u16 sb_id)		struct qed_sb_info *sb_info, u16 sb_id)
	{		{
	struct status_block *sb_virt;		struct status_block_e4 *sb_virt;
	dma_addr_t sb_phys;		dma_addr_t sb_phys;
	int rc;		int rc;

drivers/net/ethernet/qlogic/qed/qed_cxt.c

+8 −8

Original line number	Original line	Diff line number	Diff line
	@@ -86,22 +86,22 @@

	/* connection context union */		/* connection context union */
	union conn_context {		union conn_context {
	struct core_conn_context core_ctx;		struct e4_core_conn_context core_ctx;
	struct eth_conn_context eth_ctx;		struct e4_eth_conn_context eth_ctx;
	struct iscsi_conn_context iscsi_ctx;		struct e4_iscsi_conn_context iscsi_ctx;
	struct fcoe_conn_context fcoe_ctx;		struct e4_fcoe_conn_context fcoe_ctx;
	struct roce_conn_context roce_ctx;		struct e4_roce_conn_context roce_ctx;
	};		};

	/* TYPE-0 task context - iSCSI, FCOE */		/* TYPE-0 task context - iSCSI, FCOE */
	union type0_task_context {		union type0_task_context {
	struct iscsi_task_context iscsi_ctx;		struct e4_iscsi_task_context iscsi_ctx;
	struct fcoe_task_context fcoe_ctx;		struct e4_fcoe_task_context fcoe_ctx;
	};		};

	/* TYPE-1 task context - ROCE */		/* TYPE-1 task context - ROCE */
	union type1_task_context {		union type1_task_context {
	struct rdma_task_context roce_ctx;		struct e4_rdma_task_context roce_ctx;
	};		};

	struct src_ent {		struct src_ent {

drivers/net/ethernet/qlogic/qed/qed_debug.c

+56 −56

Original line number	Original line	Diff line number	Diff line
	@@ -610,9 +610,9 @@ static struct block_defs block_cnig_defs = {
	"cnig",		"cnig",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
	CNIG_REG_DBG_SELECT_K2, CNIG_REG_DBG_DWORD_ENABLE_K2,		CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
	CNIG_REG_DBG_SHIFT_K2, CNIG_REG_DBG_FORCE_VALID_K2,		CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
	CNIG_REG_DBG_FORCE_FRAME_K2,		CNIG_REG_DBG_FORCE_FRAME_K2_E5,
	true, false, DBG_RESET_REG_MISCS_PL_HV, 0		true, false, DBG_RESET_REG_MISCS_PL_HV, 0
	};		};

	@@ -654,11 +654,11 @@ static struct block_defs block_pcie_defs = {
	"pcie",		"pcie",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
	PCIE_REG_DBG_COMMON_SELECT_K2,		PCIE_REG_DBG_COMMON_SELECT_K2_E5,
	PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2,		PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
	PCIE_REG_DBG_COMMON_SHIFT_K2,		PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
	PCIE_REG_DBG_COMMON_FORCE_VALID_K2,		PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
	PCIE_REG_DBG_COMMON_FORCE_FRAME_K2,		PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
	false, false, MAX_DBG_RESET_REGS, 0		false, false, MAX_DBG_RESET_REGS, 0
	};		};

	@@ -760,9 +760,9 @@ static struct block_defs block_pglcs_defs = {
	"pglcs",		"pglcs",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
	PGLCS_REG_DBG_SELECT_K2, PGLCS_REG_DBG_DWORD_ENABLE_K2,		PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5,
	PGLCS_REG_DBG_SHIFT_K2, PGLCS_REG_DBG_FORCE_VALID_K2,		PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5,
	PGLCS_REG_DBG_FORCE_FRAME_K2,		PGLCS_REG_DBG_FORCE_FRAME_K2_E5,
	true, false, DBG_RESET_REG_MISCS_PL_HV, 2		true, false, DBG_RESET_REG_MISCS_PL_HV, 2
	};		};

	@@ -1255,9 +1255,9 @@ static struct block_defs block_umac_defs = {
	"umac",		"umac",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
	UMAC_REG_DBG_SELECT_K2, UMAC_REG_DBG_DWORD_ENABLE_K2,		UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5,
	UMAC_REG_DBG_SHIFT_K2, UMAC_REG_DBG_FORCE_VALID_K2,		UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5,
	UMAC_REG_DBG_FORCE_FRAME_K2,		UMAC_REG_DBG_FORCE_FRAME_K2_E5,
	true, false, DBG_RESET_REG_MISCS_PL_HV, 6		true, false, DBG_RESET_REG_MISCS_PL_HV, 6
	};		};

	@@ -1289,9 +1289,9 @@ static struct block_defs block_wol_defs = {
	"wol",		"wol",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
	WOL_REG_DBG_SELECT_K2, WOL_REG_DBG_DWORD_ENABLE_K2,		WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5,
	WOL_REG_DBG_SHIFT_K2, WOL_REG_DBG_FORCE_VALID_K2,		WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5,
	WOL_REG_DBG_FORCE_FRAME_K2,		WOL_REG_DBG_FORCE_FRAME_K2_E5,
	true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7		true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7
	};		};

	@@ -1299,9 +1299,9 @@ static struct block_defs block_bmbn_defs = {
	"bmbn",		"bmbn",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB},
	BMBN_REG_DBG_SELECT_K2, BMBN_REG_DBG_DWORD_ENABLE_K2,		BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5,
	BMBN_REG_DBG_SHIFT_K2, BMBN_REG_DBG_FORCE_VALID_K2,		BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5,
	BMBN_REG_DBG_FORCE_FRAME_K2,		BMBN_REG_DBG_FORCE_FRAME_K2_E5,
	false, false, MAX_DBG_RESET_REGS, 0		false, false, MAX_DBG_RESET_REGS, 0
	};		};

	@@ -1316,9 +1316,9 @@ static struct block_defs block_nwm_defs = {
	"nwm",		"nwm",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
	NWM_REG_DBG_SELECT_K2, NWM_REG_DBG_DWORD_ENABLE_K2,		NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5,
	NWM_REG_DBG_SHIFT_K2, NWM_REG_DBG_FORCE_VALID_K2,		NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5,
	NWM_REG_DBG_FORCE_FRAME_K2,		NWM_REG_DBG_FORCE_FRAME_K2_E5,
	true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0		true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0
	};		};

	@@ -1326,9 +1326,9 @@ static struct block_defs block_nws_defs = {
	"nws",		"nws",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
	NWS_REG_DBG_SELECT_K2, NWS_REG_DBG_DWORD_ENABLE_K2,		NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5,
	NWS_REG_DBG_SHIFT_K2, NWS_REG_DBG_FORCE_VALID_K2,		NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5,
	NWS_REG_DBG_FORCE_FRAME_K2,		NWS_REG_DBG_FORCE_FRAME_K2_E5,
	true, false, DBG_RESET_REG_MISCS_PL_HV, 12		true, false, DBG_RESET_REG_MISCS_PL_HV, 12
	};		};

	@@ -1336,9 +1336,9 @@ static struct block_defs block_ms_defs = {
	"ms",		"ms",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
	MS_REG_DBG_SELECT_K2, MS_REG_DBG_DWORD_ENABLE_K2,		MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5,
	MS_REG_DBG_SHIFT_K2, MS_REG_DBG_FORCE_VALID_K2,		MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5,
	MS_REG_DBG_FORCE_FRAME_K2,		MS_REG_DBG_FORCE_FRAME_K2_E5,
	true, false, DBG_RESET_REG_MISCS_PL_HV, 13		true, false, DBG_RESET_REG_MISCS_PL_HV, 13
	};		};

	@@ -1346,11 +1346,11 @@ static struct block_defs block_phy_pcie_defs = {
	"phy_pcie",		"phy_pcie",
	{false, true}, false, 0,		{false, true}, false, 0,
	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},		{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
	PCIE_REG_DBG_COMMON_SELECT_K2,		PCIE_REG_DBG_COMMON_SELECT_K2_E5,
	PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2,		PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
	PCIE_REG_DBG_COMMON_SHIFT_K2,		PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
	PCIE_REG_DBG_COMMON_FORCE_VALID_K2,		PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
	PCIE_REG_DBG_COMMON_FORCE_FRAME_K2,		PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
	false, false, MAX_DBG_RESET_REGS, 0		false, false, MAX_DBG_RESET_REGS, 0
	};		};

	@@ -1659,7 +1659,7 @@ static struct reset_reg_defs s_reset_regs_defs[] = {
	{true, true} },		{true, true} },

	/* DBG_RESET_REG_MISCS_PL_HV_2 */		/* DBG_RESET_REG_MISCS_PL_HV_2 */
	{ MISCS_REG_RESET_PL_HV_2_K2, 0x0,		{ MISCS_REG_RESET_PL_HV_2_K2_E5, 0x0,
	{false, true} },		{false, true} },

	/* DBG_RESET_REG_MISC_PL_UA */		/* DBG_RESET_REG_MISC_PL_UA */
	@@ -1685,25 +1685,25 @@ static struct reset_reg_defs s_reset_regs_defs[] = {

	static struct phy_defs s_phy_defs[] = {		static struct phy_defs s_phy_defs[] = {
	{"nw_phy", NWS_REG_NWS_CMU_K2,		{"nw_phy", NWS_REG_NWS_CMU_K2,
	PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2,		PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5,
	PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2,		PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5,
	PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2,		PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5,
	PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2},		PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5},
	{"sgmii_phy", MS_REG_MS_CMU_K2,		{"sgmii_phy", MS_REG_MS_CMU_K2_E5,
	PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2,		PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
	PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2,		PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
	PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2,		PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
	PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2},		PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
	{"pcie_phy0", PHY_PCIE_REG_PHY0_K2,		{"pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5,
	PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2,		PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
	PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2,		PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
	PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2,		PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
	PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2},		PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
	{"pcie_phy1", PHY_PCIE_REG_PHY1_K2,		{"pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5,
	PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2,		PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
	PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2,		PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
	PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2,		PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
	PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2},		PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
	};		};

	/************************** Private Functions ****************************/		/************************** Private Functions ****************************/
	@@ -1795,7 +1795,7 @@ static void qed_read_fw_info(struct qed_hwfn *p_hwfn,
	* The address is located in the last line of the Storm RAM.		* The address is located in the last line of the Storm RAM.
	*/		*/
	addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM +		addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM +
	DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE) -		DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) -
	sizeof(fw_info_location);		sizeof(fw_info_location);
	dest = (u32 *)&fw_info_location;		dest = (u32 *)&fw_info_location;

	@@ -3637,7 +3637,7 @@ static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn,
	dump,		dump,
	NULL,		NULL,
	BYTES_TO_DWORDS(MCP_REG_SCRATCH),		BYTES_TO_DWORDS(MCP_REG_SCRATCH),
	MCP_REG_SCRATCH_SIZE,		MCP_REG_SCRATCH_SIZE_BB_K2,
	false, 0, false, "MCP", false, 0);		false, 0, false, "MCP", false, 0);

	/* Dump MCP cpu_reg_file */		/* Dump MCP cpu_reg_file */

drivers/net/ethernet/qlogic/qed/qed_fcoe.c

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -115,7 +115,7 @@ qed_sp_fcoe_func_start(struct qed_hwfn *p_hwfn,
	struct qed_fcoe_pf_params *fcoe_pf_params = NULL;		struct qed_fcoe_pf_params *fcoe_pf_params = NULL;
	struct fcoe_init_ramrod_params *p_ramrod = NULL;		struct fcoe_init_ramrod_params *p_ramrod = NULL;
	struct fcoe_init_func_ramrod_data *p_data;		struct fcoe_init_func_ramrod_data *p_data;
	struct fcoe_conn_context *p_cxt = NULL;		struct e4_fcoe_conn_context *p_cxt = NULL;
	struct qed_spq_entry *p_ent = NULL;		struct qed_spq_entry *p_ent = NULL;
	struct qed_sp_init_data init_data;		struct qed_sp_init_data init_data;
	struct qed_cxt_info cxt_info;		struct qed_cxt_info cxt_info;
	@@ -167,7 +167,7 @@ qed_sp_fcoe_func_start(struct qed_hwfn *p_hwfn,
	}		}
	p_cxt = cxt_info.p_cxt;		p_cxt = cxt_info.p_cxt;
	SET_FIELD(p_cxt->tstorm_ag_context.flags3,		SET_FIELD(p_cxt->tstorm_ag_context.flags3,
	TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);		E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);

	fcoe_pf_params->dummy_icid = (u16)dummy_cid;		fcoe_pf_params->dummy_icid = (u16)dummy_cid;

	@@ -568,7 +568,7 @@ int qed_fcoe_alloc(struct qed_hwfn *p_hwfn)

	void qed_fcoe_setup(struct qed_hwfn *p_hwfn)		void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
	{		{
	struct fcoe_task_context *p_task_ctx = NULL;		struct e4_fcoe_task_context *p_task_ctx = NULL;
	int rc;		int rc;
	u32 i;		u32 i;

	@@ -580,13 +580,13 @@ void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
	if (rc)		if (rc)
	continue;		continue;

	memset(p_task_ctx, 0, sizeof(struct fcoe_task_context));		memset(p_task_ctx, 0, sizeof(struct e4_fcoe_task_context));
	SET_FIELD(p_task_ctx->timer_context.logical_client_0,		SET_FIELD(p_task_ctx->timer_context.logical_client_0,
	TIMERS_CONTEXT_VALIDLC0, 1);		TIMERS_CONTEXT_VALIDLC0, 1);
	SET_FIELD(p_task_ctx->timer_context.logical_client_1,		SET_FIELD(p_task_ctx->timer_context.logical_client_1,
	TIMERS_CONTEXT_VALIDLC1, 1);		TIMERS_CONTEXT_VALIDLC1, 1);
	SET_FIELD(p_task_ctx->tstorm_ag_context.flags0,		SET_FIELD(p_task_ctx->tstorm_ag_context.flags0,
	TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);		E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
	}		}
	}		}

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+3785 −3785

File changed.

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