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Commit 2183b499 authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915: Make power well ID names more uniform 



The format for the ID names is <platform>_DISP_PW_* so rename the IDs
not following this accordingly. Leave BXT_DPIO_CMN_BC as-is since we'll
change that to use another existing ID in the next patch.

v2:
- Fix line over 80 chars checkpatch warning.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180806095843.13294-9-imre.deak@intel.com
parent 4739a9d2

drivers/gpu/drm/i915/i915_reg.h

+5 −5
Original line number Diff line number Diff line
@@ -1036,16 +1036,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
enum i915_power_well_id {

	DISP_PW_ID_NONE,



	PUNIT_POWER_WELL_DISP2D,

	PUNIT_POWER_WELL_DPIO_CMN_BC,

	PUNIT_POWER_WELL_DPIO_CMN_D,

	VLV_DISP_PW_DISP2D,

	BXT_DISP_PW_DPIO_CMN_A,

	VLV_DISP_PW_DPIO_CMN_BC,

	GLK_DISP_PW_DPIO_CMN_C,

	CHV_DISP_PW_DPIO_CMN_D,

	HSW_DISP_PW_GLOBAL,

	SKL_DISP_PW_MISC_IO,

	SKL_DISP_PW_1,

	SKL_DISP_PW_2,

	BXT_DPIO_CMN_A,

	BXT_DPIO_CMN_BC,

	GLK_DPIO_CMN_C,

	ICL_DISP_PW_1,

	ICL_DISP_PW_2,

};

drivers/gpu/drm/i915/intel_runtime_pm.c

+23 −22
Original line number Diff line number Diff line
@@ -768,7 +768,7 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 
{

	struct i915_power_well *power_well;



	power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);

	power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);

	if (power_well->count > 0)

		bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
@@ -777,7 +777,8 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 
		bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);



	if (IS_GEMINILAKE(dev_priv)) {

		power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);

		power_well = lookup_power_well(dev_priv,

					       GLK_DISP_PW_DPIO_CMN_C);

		if (power_well->count > 0)

			bxt_ddi_phy_verify_state(dev_priv,

						 power_well->desc->bxt.phy);
@@ -1129,9 +1130,9 @@ lookup_power_well(struct drm_i915_private *dev_priv, 
static void assert_chv_phy_status(struct drm_i915_private *dev_priv)

{

	struct i915_power_well *cmn_bc =

		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);

		lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);

	struct i915_power_well *cmn_d =

		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);

		lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);

	u32 phy_control = dev_priv->chv_phy_control;

	u32 phy_status = 0;

	u32 phy_status_mask = 0xffffffff;
@@ -1241,10 +1242,10 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 
	enum pipe pipe;

	uint32_t tmp;



	WARN_ON_ONCE(power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&

		     power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_D);

	WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&

		     power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);



	if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {

	if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {

		pipe = PIPE_A;

		phy = DPIO_PHY0;

	} else {
@@ -1272,7 +1273,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 
		DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);



	if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {

	if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {

		tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);

		tmp |= DPIO_DYNPWRDOWNEN_CH1;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
@@ -1303,10 +1304,10 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 
{

	enum dpio_phy phy;



	WARN_ON_ONCE(power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&

		     power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_D);

	WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&

		     power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);



	if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {

	if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {

		phy = DPIO_PHY0;

		assert_pll_disabled(dev_priv, PIPE_A);

		assert_pll_disabled(dev_priv, PIPE_B);
@@ -2198,7 +2199,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = { 
		.name = "display",

		.domains = VLV_DISPLAY_POWER_DOMAINS,

		.ops = &vlv_display_power_well_ops,

		.id = PUNIT_POWER_WELL_DISP2D,

		.id = VLV_DISP_PW_DISP2D,

		{

			.vlv.idx = PUNIT_PWGT_IDX_DISP2D,

		},
@@ -2255,7 +2256,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = { 
		.name = "dpio-common",

		.domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,

		.ops = &vlv_dpio_cmn_power_well_ops,

		.id = PUNIT_POWER_WELL_DPIO_CMN_BC,

		.id = VLV_DISP_PW_DPIO_CMN_BC,

		{

			.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,

		},
@@ -2285,7 +2286,7 @@ static const struct i915_power_well_desc chv_power_wells[] = { 
		.name = "dpio-common-bc",

		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,

		.ops = &chv_dpio_cmn_power_well_ops,

		.id = PUNIT_POWER_WELL_DPIO_CMN_BC,

		.id = VLV_DISP_PW_DPIO_CMN_BC,

		{

			.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,

		},
@@ -2294,7 +2295,7 @@ static const struct i915_power_well_desc chv_power_wells[] = { 
		.name = "dpio-common-d",

		.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,

		.ops = &chv_dpio_cmn_power_well_ops,

		.id = PUNIT_POWER_WELL_DPIO_CMN_D,

		.id = CHV_DISP_PW_DPIO_CMN_D,

		{

			.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,

		},
@@ -2447,7 +2448,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = { 
		.name = "dpio-common-a",

		.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,

		.ops = &bxt_dpio_cmn_power_well_ops,

		.id = BXT_DPIO_CMN_A,

		.id = BXT_DISP_PW_DPIO_CMN_A,

		{

			.bxt.phy = DPIO_PHY1,

		},
@@ -2506,7 +2507,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { 
		.name = "dpio-common-a",

		.domains = GLK_DPIO_CMN_A_POWER_DOMAINS,

		.ops = &bxt_dpio_cmn_power_well_ops,

		.id = BXT_DPIO_CMN_A,

		.id = BXT_DISP_PW_DPIO_CMN_A,

		{

			.bxt.phy = DPIO_PHY1,

		},
@@ -2524,7 +2525,7 @@ static const struct i915_power_well_desc glk_power_wells[] = { 
		.name = "dpio-common-c",

		.domains = GLK_DPIO_CMN_C_POWER_DOMAINS,

		.ops = &bxt_dpio_cmn_power_well_ops,

		.id = GLK_DPIO_CMN_C,

		.id = GLK_DISP_PW_DPIO_CMN_C,

		{

			.bxt.phy = DPIO_PHY2,

		},
@@ -3627,9 +3628,9 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 
static void chv_phy_control_init(struct drm_i915_private *dev_priv)

{

	struct i915_power_well *cmn_bc =

		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);

		lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);

	struct i915_power_well *cmn_d =

		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);

		lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);



	/*

	 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
@@ -3714,9 +3715,9 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) 
static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)

{

	struct i915_power_well *cmn =

		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);

		lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);

	struct i915_power_well *disp2d =

		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);

		lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);



	/* If the display might be already active skip this */

	if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&