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Commit 217874fe authored by Gen FUKATSU's avatar Gen FUKATSU Committed by Russell King
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[ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.S 



Patch from Gen FUKATSU

Invalidate BTB entry instruction flushes two instruction
at a time. Therefore this instruction should be done four
times after invalidate instruction cache line.

Signed-off-by: Gen Fukatsu
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent a06f5466

arch/arm/mm/cache-v6.S

+8 −1
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#define HARVARD_CACHE

#define CACHE_LINE_SIZE		32

#define D_CACHE_LINE_SIZE	32

#define BTB_FLUSH_SIZE		8



/*

 *	v6_flush_cache_all()
@@ -98,7 +99,13 @@ ENTRY(v6_coherent_user_range) 
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I line

#endif

	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry

	add	r0, r0, #CACHE_LINE_SIZE

	add	r0, r0, #BTB_FLUSH_SIZE

	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry

	add	r0, r0, #BTB_FLUSH_SIZE

	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry

	add	r0, r0, #BTB_FLUSH_SIZE

	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry

	add	r0, r0, #BTB_FLUSH_SIZE

	cmp	r0, r1

	blo	1b

#ifdef HARVARD_CACHE