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Commit 215c80a7 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: meson: gxbb: add all clk81 parents 



Remove the FIXME on clk81 mux and add all the documented parents

Acked-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 46460a6b

drivers/clk/meson/gxbb.c

+8 −5
Original line number Diff line number Diff line
@@ -603,7 +603,11 @@ static struct meson_clk_mpll gxbb_mpll2 = { 
 * coordinated clock rates feature

 */



static u32 mux_table_clk81[]	= { 6, 5, 7 };

static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };

static const char * const clk81_parent_names[] = {

	"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",

	"fclk_div3", "fclk_div5"

};



static struct clk_mux gxbb_mpeg_clk_sel = {

	.reg = (void *)HHI_MPEG_CLK_CNTL,
@@ -616,13 +620,12 @@ static struct clk_mux gxbb_mpeg_clk_sel = { 
		.name = "mpeg_clk_sel",

		.ops = &clk_mux_ro_ops,

		/*

		 * FIXME bits 14:12 selects from 8 possible parents:

		 * bits 14:12 selects from 8 possible parents:

		 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,

		 * fclk_div4, fclk_div3, fclk_div5

		 */

		.parent_names = (const char *[]){ "fclk_div3", "fclk_div4",

			"fclk_div5" },

		.num_parents = 3,

		.parent_names = clk81_parent_names,

		.num_parents = ARRAY_SIZE(clk81_parent_names),

		.flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),

	},

};