Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 210bed8f authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/r600: fix offset handling in CS parser 



Need add reloc offset to the offset in the actual
packet.  Fixes use of the DRAW_INDEX packet by the 3D
driver.

[airlied: modified first one where idx_value == ib[idx+0]

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@linux.ie>
parent 2b5d6c53

drivers/gpu/drm/radeon/r600_cs.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -380,7 +380,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
			return -EINVAL;

			return -EINVAL;

		}

		}

		ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);

		ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);

		ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

		ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

		break;

		break;

	case PACKET3_DRAW_INDEX_AUTO:

	case PACKET3_DRAW_INDEX_AUTO:

		if (pkt->count != 1) {

		if (pkt->count != 1) {
@@ -408,7 +408,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
				return -EINVAL;

				return -EINVAL;

			}

			}

			ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);

			ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);

			ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

			ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

		}

		}

		break;

		break;

	case PACKET3_SURFACE_SYNC:

	case PACKET3_SURFACE_SYNC:
@@ -439,7 +439,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
				return -EINVAL;

				return -EINVAL;

			}

			}

			ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);

			ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);

			ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

			ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

		}

		}

		break;

		break;

	case PACKET3_EVENT_WRITE_EOP:

	case PACKET3_EVENT_WRITE_EOP:
@@ -453,7 +453,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
			return -EINVAL;

			return -EINVAL;

		}

		}

		ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);

		ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);

		ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

		ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

		break;

		break;

	case PACKET3_SET_CONFIG_REG:

	case PACKET3_SET_CONFIG_REG:

		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;

		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
@@ -575,7 +575,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
					return -EINVAL;

					return -EINVAL;

				}

				}

				ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);

				ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);

				ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

				ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;

				break;

				break;

			case SQ_TEX_VTX_INVALID_TEXTURE:

			case SQ_TEX_VTX_INVALID_TEXTURE:

			case SQ_TEX_VTX_INVALID_BUFFER:

			case SQ_TEX_VTX_INVALID_BUFFER: