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Commit 20fbe1a9 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "cnss2: Properly send adsp power collapse enable/disable cmds"

parents c71f313e a2261d88
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+4 −0
Original line number Diff line number Diff line
@@ -3053,6 +3053,10 @@ static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
	plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
	plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
	plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
	/* Set adsp_pc_enabled default value to true as ADSP pc is always
	 * enabled by default
	 */
	plat_priv->adsp_pc_enabled = true;
}

static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
+1 −0
Original line number Diff line number Diff line
@@ -505,6 +505,7 @@ struct cnss_plat_data {
	u32 is_converged_dt;
	struct device_node *dev_node;
	u64 feature_list;
	bool adsp_pc_enabled;
};

#ifdef CONFIG_ARCH_QCOM
+8 −0
Original line number Diff line number Diff line
@@ -1802,6 +1802,13 @@ static int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
	struct pci_dev *pci_dev = pci_priv->pci_dev;
	int ret = 0;
	u32 pm_options = PM_OPTIONS_DEFAULT;
	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;

	if (plat_priv->adsp_pc_enabled == control) {
		cnss_pr_dbg("ADSP power collapse already %s\n",
			    control ? "Enabled" : "Disabled");
		return 0;
	}

	if (control)
		pm_options &= ~MSM_PCIE_CONFIG_NO_DRV_PC;
@@ -1814,6 +1821,7 @@ static int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
		return ret;

	cnss_pr_dbg("%s ADSP power collapse\n", control ? "Enable" : "Disable");
	plat_priv->adsp_pc_enabled = control;
	return 0;
}
#else