Loading msm/dsi/dsi_ctrl_hw_cmn.c +12 −4 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ #include <linux/delay.h> Loading Loading @@ -615,15 +615,23 @@ void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl, reg |= cmd_mode_format_map[common_cfg->dst_format]; DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL, reg); if (!cfg->mdp_idle_ctrl_en) { reg = DSI_R32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2); reg |= BIT(16); DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2, reg); } reg = cfg->wr_mem_start & 0xFF; reg |= (cfg->wr_mem_continue & 0xFF) << 8; reg |= (cfg->insert_dcs_command ? BIT(16) : 0); DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL, reg); if (cfg->mdp_idle_ctrl_en) { reg = cfg->mdp_idle_ctrl_len & 0x3FF; reg |= BIT(12); DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_IDLE_CTRL, reg); } DSI_CTRL_HW_DBG(ctrl, "Cmd engine setup done\n"); } Loading msm/dsi/dsi_defs.h +6 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #ifndef _DSI_DEFS_H_ Loading Loading @@ -542,12 +542,17 @@ struct dsi_video_engine_cfg { * @wr_mem_continue: DCS command for write_memory_continue. * @insert_dcs_command: Insert DCS command as first byte of payload * of the pixel data. * @mdp_idle_ctrl_en: Enable idle insertion between command mode mdp packets. * @mdp_idle_ctrl_len: No. of dsi pclk cycles of idle time to insert between * command mode mdp packets. */ struct dsi_cmd_engine_cfg { u32 max_cmd_packets_interleave; u32 wr_mem_start; u32 wr_mem_continue; bool insert_dcs_command; bool mdp_idle_ctrl_en; u32 mdp_idle_ctrl_len; }; /** Loading msm/dsi/dsi_panel.c +15 −0 Original line number Diff line number Diff line Loading @@ -1590,6 +1590,21 @@ static int dsi_panel_parse_cmd_host_config(struct dsi_cmd_engine_cfg *cfg, goto error; } cfg->mdp_idle_ctrl_en = utils->read_bool(utils->data, "qcom,mdss-dsi-mdp-idle-ctrl-en"); if (cfg->mdp_idle_ctrl_en) { val = 0; rc = utils->read_u32(utils->data, "qcom,mdss-dsi-mdp-idle-ctrl-len", &val); if (rc) { DSI_DEBUG("[%s] mdp idle ctrl len is not defined\n", name); cfg->mdp_idle_ctrl_len = 0; cfg->mdp_idle_ctrl_en = false; rc = 0; } else { cfg->mdp_idle_ctrl_len = val; } } error: return rc; } Loading Loading
msm/dsi/dsi_ctrl_hw_cmn.c +12 −4 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ #include <linux/delay.h> Loading Loading @@ -615,15 +615,23 @@ void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl, reg |= cmd_mode_format_map[common_cfg->dst_format]; DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL, reg); if (!cfg->mdp_idle_ctrl_en) { reg = DSI_R32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2); reg |= BIT(16); DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2, reg); } reg = cfg->wr_mem_start & 0xFF; reg |= (cfg->wr_mem_continue & 0xFF) << 8; reg |= (cfg->insert_dcs_command ? BIT(16) : 0); DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL, reg); if (cfg->mdp_idle_ctrl_en) { reg = cfg->mdp_idle_ctrl_len & 0x3FF; reg |= BIT(12); DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_IDLE_CTRL, reg); } DSI_CTRL_HW_DBG(ctrl, "Cmd engine setup done\n"); } Loading
msm/dsi/dsi_defs.h +6 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #ifndef _DSI_DEFS_H_ Loading Loading @@ -542,12 +542,17 @@ struct dsi_video_engine_cfg { * @wr_mem_continue: DCS command for write_memory_continue. * @insert_dcs_command: Insert DCS command as first byte of payload * of the pixel data. * @mdp_idle_ctrl_en: Enable idle insertion between command mode mdp packets. * @mdp_idle_ctrl_len: No. of dsi pclk cycles of idle time to insert between * command mode mdp packets. */ struct dsi_cmd_engine_cfg { u32 max_cmd_packets_interleave; u32 wr_mem_start; u32 wr_mem_continue; bool insert_dcs_command; bool mdp_idle_ctrl_en; u32 mdp_idle_ctrl_len; }; /** Loading
msm/dsi/dsi_panel.c +15 −0 Original line number Diff line number Diff line Loading @@ -1590,6 +1590,21 @@ static int dsi_panel_parse_cmd_host_config(struct dsi_cmd_engine_cfg *cfg, goto error; } cfg->mdp_idle_ctrl_en = utils->read_bool(utils->data, "qcom,mdss-dsi-mdp-idle-ctrl-en"); if (cfg->mdp_idle_ctrl_en) { val = 0; rc = utils->read_u32(utils->data, "qcom,mdss-dsi-mdp-idle-ctrl-len", &val); if (rc) { DSI_DEBUG("[%s] mdp idle ctrl len is not defined\n", name); cfg->mdp_idle_ctrl_len = 0; cfg->mdp_idle_ctrl_en = false; rc = 0; } else { cfg->mdp_idle_ctrl_len = val; } } error: return rc; } Loading