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Commit 20ef6d06 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-11-11' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "drm: i915, amdgpu, sun4i, exynos and etnaviv fixes:

   - amdgpu has some display fixes, KFD ioctl fixes and a Vega20 bios
     interaction fix.

   - sun4i has some NULL checks added

   - i915 has a 32-bit system fix, LPE audio oops, and HDMI2.0 clock
     fixes.

   - Exynos has a 3 regression fixes (one frame counter, fbdev missing,
     dsi->panel check)

   - Etnaviv has a single fencing fix for GPU recovery"

* tag 'drm-fixes-2018-11-11' of git://anongit.freedesktop.org/drm/drm: (39 commits)
  drm/amd/amdgpu/dm: Fix dm_dp_create_fake_mst_encoder()
  drm/amd/display: Drop reusing drm connector for MST
  drm/amd/display: Cleanup MST non-atomic code workaround
  drm/amd/powerplay: always use fast UCLK switching when UCLK DPM enabled
  drm/amd/powerplay: set a default fclk/gfxclk ratio
  drm/amdgpu/display/dce11: only enable FBC when selected
  drm/amdgpu/display/dm: handle FBC dc feature parameter
  drm/amdgpu/display/dc: add FBC to dc_config
  drm/amdgpu: add DC feature mask module parameter
  drm/amdgpu/display: check if fbc is available in set_static_screen_control (v2)
  drm/amdgpu/vega20: add CLK base offset
  drm/amd/display: Stop leaking planes
  drm/amd/display: Fix misleading buffer information
  Revert "drm/amd/display: set backlight level limit to 1"
  drm/amd: Update atom_smu_info_v3_3 structure
  drm/i915: Fix ilk+ watermarks when disabling pipes
  drm/sun4i: tcon: prevent tcon->panel dereference if NULL
  drm/sun4i: tcon: fix check of tcon->panel null pointer
  drm/i915: Don't oops during modeset shutdown after lpe audio deinit
  drm/i915: Mark pin flags as u64
  ...
parents 1de4f2ef 73b6f96c

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -151,6 +151,7 @@ extern int amdgpu_compute_multipipe; 
extern int amdgpu_gpu_recovery;

extern int amdgpu_emu_mode;

extern uint amdgpu_smu_memory_pool_size;

extern uint amdgpu_dc_feature_mask;

extern struct amdgpu_mgpu_info mgpu_info;



#ifdef CONFIG_DRM_AMDGPU_SI

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+11 −0
Original line number Diff line number Diff line
@@ -127,6 +127,9 @@ int amdgpu_compute_multipipe = -1; 
int amdgpu_gpu_recovery = -1; /* auto */

int amdgpu_emu_mode = 0;

uint amdgpu_smu_memory_pool_size = 0;

/* FBC (bit 0) disabled by default*/

uint amdgpu_dc_feature_mask = 0;



struct amdgpu_mgpu_info mgpu_info = {

	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),

};
@@ -631,6 +634,14 @@ module_param(halt_if_hws_hang, int, 0644); 
MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");

#endif



/**

 * DOC: dcfeaturemask (uint)

 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.

 * The default is the current set of stable display features.

 */

MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");

module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);



static const struct pci_device_id pciidlist[] = {

#ifdef  CONFIG_DRM_AMDGPU_SI

	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},

drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev) 
		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

	}

	return 0;

}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+8 −19
Original line number Diff line number Diff line
@@ -429,6 +429,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 
	    adev->asic_type < CHIP_RAVEN)

		init_data.flags.gpu_vm_support = true;



	if (amdgpu_dc_feature_mask & DC_FBC_MASK)

		init_data.flags.fbc_support = true;



	/* Display Core create. */

	adev->dm.dc = dc_create(&init_data);
@@ -1524,13 +1527,6 @@ static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 
{

	struct amdgpu_display_manager *dm = bl_get_data(bd);



	/*

	 * PWM interperts 0 as 100% rather than 0% because of HW

	 * limitation for level 0.So limiting minimum brightness level

	 * to 1.

	 */

	if (bd->props.brightness < 1)

		return 1;

	if (dc_link_set_backlight_level(dm->backlight_link,

			bd->props.brightness, 0, 0))

		return 0;
@@ -2707,18 +2703,11 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
	drm_connector = &aconnector->base;



	if (!aconnector->dc_sink) {

		/*

		 * Create dc_sink when necessary to MST

		 * Don't apply fake_sink to MST

		 */

		if (aconnector->mst_port) {

			dm_dp_mst_dc_sink_create(drm_connector);

			return stream;

		}



		if (!aconnector->mst_port) {

			sink = create_fake_sink(aconnector);

			if (!sink)

				return stream;

		}

	} else {

		sink = aconnector->dc_sink;

	}
@@ -3308,7 +3297,7 @@ void dm_drm_plane_destroy_state(struct drm_plane *plane, 
static const struct drm_plane_funcs dm_plane_funcs = {

	.update_plane	= drm_atomic_helper_update_plane,

	.disable_plane	= drm_atomic_helper_disable_plane,

	.destroy	= drm_plane_cleanup,

	.destroy	= drm_primary_helper_destroy,

	.reset = dm_drm_plane_reset,

	.atomic_duplicate_state = dm_drm_plane_duplicate_state,

	.atomic_destroy_state = dm_drm_plane_destroy_state,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+0 −2
Original line number Diff line number Diff line
@@ -160,8 +160,6 @@ struct amdgpu_dm_connector { 
	struct mutex hpd_lock;



	bool fake_enable;



	bool mst_connected;

};



#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)