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Commit 20e88ced authored by Pankaj Gupta's avatar Pankaj Gupta
Browse files

ARM: dts: msm: Add GPU properties for Blair 

Add chip id and update GPU power levels for blair GPU.

Change-Id: I14a4995dcd178df1ff91257a1b93e809dd6ed5e2
parent 6e8c860b

qcom/blair.dtsi

+276 −0
Original line number Diff line number Diff line
@@ -3438,4 +3438,280 @@ 
	status = "ok";

};



&msm_gpu {

	qcom,chipid = <0x06010901>;



	/delete-node/qcom,gpu-pwrlevel-bins;



	/*

	 * Speed-bin zero is default speed bin.

	 * For rest of the speed bins, speed-bin value

	 * is calulated as FMAX/4.8 MHz (round up to zero

	 * decimal places) + 2.

	 */

	qcom,gpu-pwrlevel-bins {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevel-bins";



		qcom,gpu-pwrlevels-0 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <0>;

			qcom,ca-target-pwrlevel = <5>;

			qcom,initial-pwrlevel = <6>;



			/* TURBO_L1 */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <900000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;



				qcom,bus-freq-ddr7 = <9>;

				qcom,bus-min-ddr7 = <8>;

				qcom,bus-max-ddr7 = <9>;

			};



			/* TURBO */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <840000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <7>;

				qcom,bus-max-ddr7 = <9>;



			};



			/* NOM_L1 */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <770000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



				qcom,bus-freq-ddr7 = <7>;

				qcom,bus-min-ddr7 = <5>;

				qcom,bus-max-ddr7 = <9>;



			};



			/* NOM */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;



				qcom,bus-freq-ddr7 = <6>;

				qcom,bus-min-ddr7 = <5>;

				qcom,bus-max-ddr7 = <8>;



			};



			/* SVS_L1 */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <490000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;



				qcom,bus-freq-ddr7 = <5>;

				qcom,bus-min-ddr7 = <4>;

				qcom,bus-max-ddr7 = <7>;



			};



			/* SVS */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <390000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;



				qcom,bus-freq-ddr7 = <4>;

				qcom,bus-min-ddr7 = <2>;

				qcom,bus-max-ddr7= <5>;

			};



			/* LOW SVS */

			qcom,gpu-pwrlevel@6 {

				reg = <6>;

				qcom,gpu-freq = <266000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;



				qcom,bus-freq-ddr7 = <2>;

				qcom,bus-min-ddr7 = <1>;

				qcom,bus-max-ddr7 = <4>;

			};



		};



		qcom,gpu-pwrlevels-1 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <190>;

			qcom,ca-target-pwrlevel = <5>;

			qcom,initial-pwrlevel = <6>;



			/* TURBO_L1 */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <900000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;



				qcom,bus-freq-ddr7 = <9>;

				qcom,bus-min-ddr7 = <8>;

				qcom,bus-max-ddr7 = <9>;

			};



			/* TURBO */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <840000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <7>;

				qcom,bus-max-ddr7 = <9>;



			};



			/* NOM_L1 */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <770000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



				qcom,bus-freq-ddr7 = <7>;

				qcom,bus-min-ddr7 = <5>;

				qcom,bus-max-ddr7 = <9>;



			};



			/* NOM */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;



				qcom,bus-freq-ddr7 = <6>;

				qcom,bus-min-ddr7 = <5>;

				qcom,bus-max-ddr7 = <8>;



			};



			/* SVS_L1 */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <490000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;



				qcom,bus-freq-ddr7 = <5>;

				qcom,bus-min-ddr7 = <4>;

				qcom,bus-max-ddr7 = <7>;



			};



			/* SVS */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <390000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;



				qcom,bus-freq-ddr7 = <4>;

				qcom,bus-min-ddr7 = <2>;

				qcom,bus-max-ddr7= <5>;

			};



			/* LOW SVS */

			qcom,gpu-pwrlevel@6 {

				reg = <6>;

				qcom,gpu-freq = <266000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;



				qcom,bus-freq-ddr7 = <2>;

				qcom,bus-min-ddr7 = <1>;

				qcom,bus-max-ddr7 = <4>;

			};



		};



		qcom,gpu-pwrlevels-2 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <177>;

			qcom,ca-target-pwrlevel = <4>;

			qcom,initial-pwrlevel = <5>;



			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <840000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <7>;

				qcom,bus-max-ddr7 = <9>;



			};



			/* NOM_L1 */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <770000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



				qcom,bus-freq-ddr7 = <7>;

				qcom,bus-min-ddr7 = <5>;

				qcom,bus-max-ddr7 = <9>;



			};



			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;



				qcom,bus-freq-ddr7 = <6>;

				qcom,bus-min-ddr7 = <5>;

				qcom,bus-max-ddr7 = <8>;



			};



			/* SVS_L1 */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <490000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;



				qcom,bus-freq-ddr7 = <5>;

				qcom,bus-min-ddr7 = <4>;

				qcom,bus-max-ddr7 = <7>;



			};



			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <390000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;



				qcom,bus-freq-ddr7 = <4>;

				qcom,bus-min-ddr7 = <2>;

				qcom,bus-max-ddr7= <5>;

			};



			/* LOW SVS */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <266000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;



				qcom,bus-freq-ddr7 = <2>;

				qcom,bus-min-ddr7 = <1>;

				qcom,bus-max-ddr7 = <4>;

			};

		};

	};

};



#include "msm-rdbg.dtsi"