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Commit 20895190 authored by Saurabh Sahu's avatar Saurabh Sahu
Browse files

dt-bindings: clock: Add support for clock ids for MONACO 



Add clock ids for GCC/DISPCC/GPUCC for clients to be able
to request for clocks from these clock controllers for
monaco.

Change-Id: Ie09a5a7a5fd1101fb863e836a0e554198e699511
Signed-off-by: default avatarSaurabh Sahu <sausah@codeaurora.org>
parent 6998de7d

include/dt-bindings/clock/qcom,dispcc-monaco.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_MONACO_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_MONACO_H



/* DISP_CC clocks */

#define DISP_CC_MDSS_AHB_CLK			0

#define DISP_CC_MDSS_AHB_CLK_SRC		1

#define DISP_CC_MDSS_BYTE0_CLK			2

#define DISP_CC_MDSS_BYTE0_CLK_SRC		3

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC		4

#define DISP_CC_MDSS_BYTE0_INTF_CLK		5

#define DISP_CC_MDSS_ESC0_CLK			6

#define DISP_CC_MDSS_ESC0_CLK_SRC		7

#define DISP_CC_MDSS_MDP_CLK			8

#define DISP_CC_MDSS_MDP_CLK_SRC		9

#define DISP_CC_MDSS_MDP_LUT_CLK		10

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK		11

#define DISP_CC_MDSS_PCLK0_CLK			12

#define DISP_CC_MDSS_PCLK0_CLK_SRC		13

#define DISP_CC_MDSS_VSYNC_CLK			14

#define DISP_CC_MDSS_VSYNC_CLK_SRC		15

#define DISP_CC_SLEEP_CLK			16

#define DISP_CC_SLEEP_CLK_SRC			17

#define DISP_CC_XO_CLK				18

#define DISP_CC_XO_CLK_SRC			19



#endif

include/dt-bindings/clock/qcom,gcc-monaco.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GCC_MONACO_H

#define _DT_BINDINGS_CLK_QCOM_GCC_MONACO_H



/* GCC clocks */

#define GPLL0					0

#define GPLL0_OUT_EVEN				1

#define GPLL1					2

#define GPLL10					3

#define GPLL3					4

#define GPLL3_OUT_EVEN				5

#define GPLL4					6

#define GPLL6					7

#define GPLL6_OUT_EVEN				8

#define GPLL7					9

#define GPLL8					10

#define GPLL8_OUT_EVEN				11

#define GPLL9					12

#define GPLL9_OUT_EVEN				13

#define GCC_AHB2PHY_CSI_CLK			14

#define GCC_AHB2PHY_USB_CLK			15

#define GCC_BIMC_GPU_AXI_CLK			16

#define GCC_BOOT_ROM_AHB_CLK			17

#define GCC_CAM_THROTTLE_NRT_CLK		18

#define GCC_CAM_THROTTLE_RT_CLK			19

#define GCC_CAMERA_AHB_CLK			20

#define GCC_CAMERA_XO_CLK			21

#define GCC_CAMSS_AXI_CLK			22

#define GCC_CAMSS_AXI_CLK_SRC			23

#define GCC_CAMSS_CAMNOC_ATB_CLK		24

#define GCC_CAMSS_CAMNOC_NTS_XO_CLK		25

#define GCC_CAMSS_CCI_0_CLK			26

#define GCC_CAMSS_CCI_CLK_SRC			27

#define GCC_CAMSS_CPHY_0_CLK			28

#define GCC_CAMSS_CPHY_1_CLK			29

#define GCC_CAMSS_CSI0PHYTIMER_CLK		30

#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC		31

#define GCC_CAMSS_CSI1PHYTIMER_CLK		32

#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC		33

#define GCC_CAMSS_MCLK0_CLK			34

#define GCC_CAMSS_MCLK0_CLK_SRC			35

#define GCC_CAMSS_MCLK1_CLK			36

#define GCC_CAMSS_MCLK1_CLK_SRC			37

#define GCC_CAMSS_MCLK2_CLK			38

#define GCC_CAMSS_MCLK2_CLK_SRC			39

#define GCC_CAMSS_MCLK3_CLK			40

#define GCC_CAMSS_MCLK3_CLK_SRC			41

#define GCC_CAMSS_NRT_AXI_CLK			42

#define GCC_CAMSS_OPE_AHB_CLK			43

#define GCC_CAMSS_OPE_AHB_CLK_SRC		44

#define GCC_CAMSS_OPE_CLK			45

#define GCC_CAMSS_OPE_CLK_SRC			46

#define GCC_CAMSS_RT_AXI_CLK			47

#define GCC_CAMSS_TFE_0_CLK			48

#define GCC_CAMSS_TFE_0_CLK_SRC			49

#define GCC_CAMSS_TFE_0_CPHY_RX_CLK		50

#define GCC_CAMSS_TFE_0_CSID_CLK		51

#define GCC_CAMSS_TFE_0_CSID_CLK_SRC		52

#define GCC_CAMSS_TFE_1_CLK			53

#define GCC_CAMSS_TFE_1_CLK_SRC			54

#define GCC_CAMSS_TFE_1_CPHY_RX_CLK		55

#define GCC_CAMSS_TFE_1_CSID_CLK		56

#define GCC_CAMSS_TFE_1_CSID_CLK_SRC		57

#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC		58

#define GCC_CAMSS_TOP_AHB_CLK			59

#define GCC_CAMSS_TOP_AHB_CLK_SRC		60

#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK		61

#define GCC_CPUSS_AHB_CLK_SRC			62

#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC		63

#define GCC_CPUSS_GNOC_CLK			64

#define GCC_DISP_AHB_CLK			65

#define GCC_DISP_GPLL0_CLK_SRC			66

#define GCC_DISP_HF_AXI_CLK			67

#define GCC_DISP_THROTTLE_CORE_CLK		68

#define GCC_DISP_XO_CLK				69

#define GCC_GP1_CLK				70

#define GCC_GP1_CLK_SRC				71

#define GCC_GP2_CLK				72

#define GCC_GP2_CLK_SRC				73

#define GCC_GP3_CLK				74

#define GCC_GP3_CLK_SRC				75

#define GCC_GPU_CFG_AHB_CLK			76

#define GCC_GPU_GPLL0_CLK_SRC			77

#define GCC_GPU_GPLL0_DIV_CLK_SRC		78

#define GCC_GPU_IREF_CLK			79

#define GCC_GPU_MEMNOC_GFX_CLK			80

#define GCC_GPU_SNOC_DVM_GFX_CLK		81

#define GCC_GPU_THROTTLE_CORE_CLK		82

#define GCC_PDM2_CLK				83

#define GCC_PDM2_CLK_SRC			84

#define GCC_PDM_AHB_CLK				85

#define GCC_PDM_XO4_CLK				86

#define GCC_PWM0_XO512_CLK			87

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		88

#define GCC_QMIP_CAMERA_RT_AHB_CLK		89

#define GCC_QMIP_DISP_AHB_CLK			90

#define GCC_QMIP_GPU_CFG_AHB_CLK		91

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		92

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		93

#define GCC_QUPV3_WRAP0_CORE_CLK		94

#define GCC_QUPV3_WRAP0_S0_CLK			95

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		96

#define GCC_QUPV3_WRAP0_S1_CLK			97

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		98

#define GCC_QUPV3_WRAP0_S2_CLK			99

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		100

#define GCC_QUPV3_WRAP0_S3_CLK			101

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		102

#define GCC_QUPV3_WRAP0_S4_CLK			103

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		104

#define GCC_QUPV3_WRAP0_S5_CLK			105

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		106

#define GCC_QUPV3_WRAP0_S6_CLK			107

#define GCC_QUPV3_WRAP0_S6_CLK_SRC		108

#define GCC_QUPV3_WRAP0_S7_CLK			109

#define GCC_QUPV3_WRAP0_S7_CLK_SRC		110

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		111

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		112

#define GCC_SDCC1_AHB_CLK			113

#define GCC_SDCC1_APPS_CLK			114

#define GCC_SDCC1_APPS_CLK_SRC			115

#define GCC_SDCC1_ICE_CORE_CLK			116

#define GCC_SDCC1_ICE_CORE_CLK_SRC		117

#define GCC_SDCC2_AHB_CLK			118

#define GCC_SDCC2_APPS_CLK			119

#define GCC_SDCC2_APPS_CLK_SRC			120

#define GCC_SYS_NOC_CPUSS_AHB_CLK		121

#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK		122

#define GCC_USB20_MASTER_CLK			123

#define GCC_USB20_MASTER_CLK_SRC		124

#define GCC_USB20_MOCK_UTMI_CLK			125

#define GCC_USB20_MOCK_UTMI_CLK_SRC		126

#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC	127

#define GCC_USB20_SLEEP_CLK			128

#define GCC_VCODEC0_AXI_CLK			129

#define GCC_VENUS_AHB_CLK			130

#define GCC_VENUS_CTL_AXI_CLK			131

#define GCC_VIDEO_AHB_CLK			132

#define GCC_VIDEO_THROTTLE_CORE_CLK		133

#define GCC_VIDEO_VCODEC0_SYS_CLK		134

#define GCC_VIDEO_VENUS_CLK_SRC			135

#define GCC_VIDEO_VENUS_CTL_CLK			136

#define GCC_VIDEO_XO_CLK			137



/* GCC resets */

#define GCC_CAMSS_OPE_BCR			0

#define GCC_CAMSS_TFE_BCR			1

#define GCC_CAMSS_TOP_BCR			2

#define GCC_GPU_BCR				3

#define GCC_MMSS_BCR				4

#define GCC_PDM_BCR				5

#define GCC_QUPV3_WRAPPER_0_BCR			6

#define GCC_QUSB2PHY_PRIM_BCR			7

#define GCC_QUSB2PHY_SEC_BCR			8

#define GCC_SDCC1_BCR				9

#define GCC_SDCC2_BCR				10

#define GCC_USB20_PRIM_BCR			11

#define GCC_USB_PHY_CFG_AHB2PHY_BCR		12

#define GCC_VCODEC0_BCR				13

#define GCC_VENUS_BCR				14

#define GCC_VIDEO_INTERFACE_BCR			15



#endif

include/dt-bindings/clock/qcom,gpucc-monaco.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_MONACO_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_MONACO_H



/* GPU_CC clocks */

#define GPU_CC_PLL0			0

#define GPU_CC_AHB_CLK			1

#define GPU_CC_CRC_AHB_CLK		2

#define GPU_CC_CX_APB_CLK		3

#define GPU_CC_CX_GFX3D_CLK		4

#define GPU_CC_CX_GFX3D_SLV_CLK		5

#define GPU_CC_CX_GMU_CLK		6

#define GPU_CC_CX_SNOC_DVM_CLK		7

#define GPU_CC_CXO_AON_CLK		8

#define GPU_CC_CXO_AON_CLK_SRC		9

#define GPU_CC_CXO_CLK			10

#define GPU_CC_GMU_CLK_SRC		11

#define GPU_CC_GX_CXO_CLK		12

#define GPU_CC_GX_GFX3D_CLK		13

#define GPU_CC_GX_GFX3D_CLK_SRC		14

#define GPU_CC_SLEEP_CLK		15

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK	16



#endif