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Commit 208937fd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Thomas Gleixner:

 - a bugfix which prevents a divide by 0 panic when the newly introduced
   try_msr_calibrate_tsc() fails

 - enablement of the Baytrail platform to utilize the newfangled msr
   based calibration

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86: tsc: Add missing Baytrail frequency to the table
  x86, tsc: Fallback to normal calibration if fast MSR calibration fails
parents 5fe37fcf 3e11e818

arch/x86/include/asm/tsc.h

+1 −1
Original line number Diff line number Diff line
@@ -66,6 +66,6 @@ extern void tsc_save_sched_clock_state(void); 
extern void tsc_restore_sched_clock_state(void);



/* MSR based TSC calibration for Intel Atom SoC platforms */

int try_msr_calibrate_tsc(unsigned long *fast_calibrate);

unsigned long try_msr_calibrate_tsc(void);



#endif /* _ASM_X86_TSC_H */

arch/x86/kernel/tsc.c

+2 −5
Original line number Diff line number Diff line
@@ -653,13 +653,10 @@ unsigned long native_calibrate_tsc(void) 


	/* Calibrate TSC using MSR for Intel Atom SoCs */

	local_irq_save(flags);

	i = try_msr_calibrate_tsc(&fast_calibrate);

	fast_calibrate = try_msr_calibrate_tsc();

	local_irq_restore(flags);

	if (i >= 0) {

		if (i == 0)

			pr_warn("Fast TSC calibration using MSR failed\n");

	if (fast_calibrate)

		return fast_calibrate;

	}



	local_irq_save(flags);

	fast_calibrate = quick_pit_calibrate();

arch/x86/kernel/tsc_msr.c

+15 −15
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static struct freq_desc freq_desc_tables[] = { 
	/* TNG */

	{ 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },

	/* VLV2 */

	{ 6, 0x37, 1, { 0, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },

	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },

	/* ANN */

	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },

};
@@ -77,21 +77,18 @@ static int match_cpu(u8 family, u8 model) 


/*

 * Do MSR calibration only for known/supported CPUs.

 * Return values:

 * -1: CPU is unknown/unsupported for MSR based calibration

 *  0: CPU is known/supported, but calibration failed

 *  1: CPU is known/supported, and calibration succeeded

 *

 * Returns the calibration value or 0 if MSR calibration failed.

 */

int try_msr_calibrate_tsc(unsigned long *fast_calibrate)

unsigned long try_msr_calibrate_tsc(void)

{

	int cpu_index;

	u32 lo, hi, ratio, freq_id, freq;

	unsigned long res;

	int cpu_index;



	cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);

	if (cpu_index < 0)

		return -1;



	*fast_calibrate = 0;

		return 0;



	if (freq_desc_tables[cpu_index].msr_plat) {

		rdmsr(MSR_PLATFORM_INFO, lo, hi);
@@ -103,7 +100,7 @@ int try_msr_calibrate_tsc(unsigned long *fast_calibrate) 
	pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);



	if (!ratio)

		return 0;

		goto fail;



	/* Get FSB FREQ ID */

	rdmsr(MSR_FSB_FREQ, lo, hi);
@@ -112,16 +109,19 @@ int try_msr_calibrate_tsc(unsigned long *fast_calibrate) 
	pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",

				freq_id, freq);

	if (!freq)

		return 0;

		goto fail;



	/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */

	*fast_calibrate = freq * ratio;

	pr_info("TSC runs at %lu KHz\n", *fast_calibrate);

	res = freq * ratio;

	pr_info("TSC runs at %lu KHz\n", res);



#ifdef CONFIG_X86_LOCAL_APIC

	lapic_timer_frequency = (freq * 1000) / HZ;

	pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);

#endif

	return res;



	return 1;

fail:

	pr_warn("Fast TSC calibration using MSR failed\n");

	return 0;

}