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Commit 20848223 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
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drm/i915: set IDICOS to medium uncore resources 



I'm seeing about a 5% FPS improvement across various benchmarks on my
IVB i3. Rumor has it that the higher end parts show even more benefit.

This derives from a patch originally given to me by Bernard. The docs
are  confusing about the definition names (ie. medium really seems like
max), but it would seem it gives more cache to the GT at the expense of
uncore. This configuration makes the split most in favor of the GT. I've
not tried the other IDICOS values.

Cc: "Kilarski, Bernard R" <bernard.r.kilarski@intel.com>
Acked-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e158c5aa

drivers/gpu/drm/i915/intel_pm.c

+6 −0
Original line number Diff line number Diff line
@@ -3384,6 +3384,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;

	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

	uint32_t snpcr;



	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
@@ -3429,6 +3430,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	/* WaDisable4x2SubspanOptimization */

	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));



	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);

	snpcr &= ~GEN6_MBC_SNPCR_MASK;

	snpcr |= GEN6_MBC_SNPCR_MED;

	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);

}



static void valleyview_init_clock_gating(struct drm_device *dev)