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Commit 207083b1 authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Markos Chandras
Browse files

MIPS: kernel: r4k_switch: Add support for MIPS R6 



Add the MIPS R6 related preprocessor definitions for save/restore
FPU related functions. We also set the appropriate ISA level
so the final return instruction "jr ra" will produce the correct
opcode on R6.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent 9c7d5768

arch/mips/include/asm/asmmacro.h

+7 −5
Original line number Diff line number Diff line
@@ -104,7 +104,8 @@ 
	.endm



	.macro	fpu_save_double thread status tmp

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \

		defined(CONFIG_CPU_MIPS32_R6)

	sll	\tmp, \status, 5

	bgez	\tmp, 10f

	fpu_save_16odd \thread
@@ -160,7 +161,8 @@ 
	.endm



	.macro	fpu_restore_double thread status tmp

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \

		defined(CONFIG_CPU_MIPS32_R6)

	sll	\tmp, \status, 5

	bgez	\tmp, 10f				# 16 register mode?
@@ -170,16 +172,16 @@ 
	fpu_restore_16even \thread \tmp

	.endm



#ifdef CONFIG_CPU_MIPSR2

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

	.macro	_EXT	rd, rs, p, s

	ext	\rd, \rs, \p, \s

	.endm

#else /* !CONFIG_CPU_MIPSR2 */

#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */

	.macro	_EXT	rd, rs, p, s

	srl	\rd, \rs, \p

	andi	\rd, \rd, (1 << \s) - 1

	.endm

#endif /* !CONFIG_CPU_MIPSR2 */

#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */



/*

 * Temporary until all gas have MT ASE support

arch/mips/kernel/r4k_switch.S

+8 −6
Original line number Diff line number Diff line
@@ -115,7 +115,8 @@ 
 * Save a thread's fp context.

 */

LEAF(_save_fp)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \

		defined(CONFIG_CPU_MIPS32_R6)

	mfc0	t0, CP0_STATUS

#endif

	fpu_save_double a0 t0 t1		# clobbers t1
@@ -126,7 +127,8 @@ LEAF(_save_fp) 
 * Restore a thread's fp context.

 */

LEAF(_restore_fp)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \

		defined(CONFIG_CPU_MIPS32_R6)

	mfc0	t0, CP0_STATUS

#endif

	fpu_restore_double a0 t0 t1		# clobbers t1
@@ -240,9 +242,9 @@ LEAF(_init_fpu) 
	mtc1	t1, $f30

	mtc1	t1, $f31



#ifdef CONFIG_CPU_MIPS32_R2

#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)

	.set    push

	.set    mips32r2

	.set    MIPS_ISA_LEVEL_RAW

	.set	fp=64

	sll     t0, t0, 5			# is Status.FR set?

	bgez    t0, 1f				# no: skip setting upper 32b
@@ -280,9 +282,9 @@ LEAF(_init_fpu) 
	mthc1   t1, $f30

	mthc1   t1, $f31

1:	.set    pop

#endif /* CONFIG_CPU_MIPS32_R2 */

#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */

#else

	.set	arch=r4000

	.set	MIPS_ISA_ARCH_LEVEL_RAW

	dmtc1	t1, $f0

	dmtc1	t1, $f2

	dmtc1	t1, $f4