Commit 200e0dd1 authored Feb 07, 2020 by Ritesh Harjani Committed by Sarthak Garg Aug 10, 2020

UPSTREAM: mmc: sdhci-msm: Don't enable PWRSAVE_DLL for certain sdhc hosts



SDHC core with new 14lpp and later tech DLL should not enable
PWRSAVE_DLL since such controller's internal gating cannot meet
following MCLK requirement:
When MCLK is gated OFF, it is not gated for less than 0.5us and MCLK
must be switched on for at-least 1us before DATA starts coming.

Adding support for this requirement.

Change-Id: I571c8fb40835e094d8feb4df5c2d049c02a0a2f2
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Reviewed-by: Can Guo <cang@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/1581077075-26011-1-git-send-email-vbadigan@codeaurora.org


Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>

parent 5827a3e5

drivers/mmc/host/sdhci-msm.c

+15 −3

Original line number	Diff line number	Diff line
		@@ -1224,9 +1224,21 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
		goto out;
		}

		config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
		/*
		* Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
		* When MCLK is gated OFF, it is not gated for less than 0.5us
		* and MCLK must be switched on for at-least 1us before DATA
		* starts coming. Controllers with 14lpp and later tech DLL cannot
		* guarantee above requirement. So PWRSAVE_DLL should not be
		* turned on for host controllers using this DLL.
		*/
		if (!msm_host->use_14lpp_dll_reset) {
		config = readl_relaxed(host->ioaddr +
		msm_offset->core_vendor_spec3);
		config \|= CORE_PWRSAVE_DLL;
		writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
		writel_relaxed(config, host->ioaddr +
		msm_offset->core_vendor_spec3);
		}

		/*
		* Drain writebuffer to ensure above DLL calibration