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Commit 1fa725da authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: lahaina: Add pll test ctl regs"

parents 732adf0e 7c45d69c

drivers/clk/qcom/camcc-lahaina.c

+24 −6
Original line number Diff line number Diff line
@@ -62,7 +62,10 @@ static const struct alpha_pll_config cam_cc_pll0_config = { 
	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00003100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -147,7 +150,10 @@ static const struct alpha_pll_config cam_cc_pll1_config = { 
	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -245,7 +251,10 @@ static const struct alpha_pll_config cam_cc_pll3_config = { 
	.alpha = 0x3555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -307,7 +316,10 @@ static const struct alpha_pll_config cam_cc_pll4_config = { 
	.alpha = 0x3555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -369,7 +381,10 @@ static const struct alpha_pll_config cam_cc_pll5_config = { 
	.alpha = 0x3555,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -431,7 +446,10 @@ static const struct alpha_pll_config cam_cc_pll6_config = { 
	.alpha = 0x0,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

drivers/clk/qcom/debugcc-lahaina.c

+16 −0
Original line number Diff line number Diff line
@@ -454,6 +454,14 @@ static const char *const gcc_debug_mux_parent_names[] = { 
	"measure_only_ipa_2x_clk",

	"measure_only_memnoc_clk",

	"measure_only_snoc_clk",

	"pcie_0_pipe_clk",

	"pcie_1_pipe_clk",

	"ufs_card_rx_symbol_0_clk",

	"ufs_card_rx_symbol_1_clk",

	"ufs_card_tx_symbol_0_clk",

	"ufs_phy_rx_symbol_0_clk",

	"ufs_phy_rx_symbol_1_clk",

	"ufs_phy_tx_symbol_0_clk",

	"usb3_phy_wrapper_gcc_usb30_pipe_clk",

	"usb3_uni_phy_sec_gcc_usb30_pipe_clk",

	"video_cc_debug_mux",
@@ -591,6 +599,14 @@ static int gcc_debug_mux_sels[] = { 
	0x140,		/* measure_only_ipa_2x_clk */

	0xCF,		/* measure_only_memnoc_clk */

	0x9,		/* measure_only_snoc_clk */

	0xFB,		/* pcie_0_pipe_clk */

	0x104,		/* pcie_1_pipe_clk */

	0x10B,		/* ufs_card_rx_symbol_0_clk */

	0x110,		/* ufs_card_rx_symbol_1_clk */

	0x10A,		/* ufs_card_tx_symbol_0_clk */

	0x117,		/* ufs_phy_rx_symbol_0_clk */

	0x11C,		/* ufs_phy_rx_symbol_1_clk */

	0x116,		/* ufs_phy_tx_symbol_0_clk */

	0x7C,		/* usb3_phy_wrapper_gcc_usb30_pipe_clk */

	0x7D,		/* usb3_uni_phy_sec_gcc_usb30_pipe_clk */

	0x5A,		/* video_cc_debug_mux */

drivers/clk/qcom/dispcc-lahaina.c

+8 −2
Original line number Diff line number Diff line
@@ -63,7 +63,10 @@ static const struct alpha_pll_config disp_cc_pll0_config = { 
	.alpha = 0xE000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -102,7 +105,10 @@ static const struct alpha_pll_config disp_cc_pll1_config = { 
	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,

drivers/clk/qcom/gpucc-lahaina.c

+27 −10
Original line number Diff line number Diff line
@@ -25,9 +25,11 @@ 
#include "vdd-level.h"



static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NOMINAL + 1, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NOMINAL + 1, 1, vdd_corner);



static struct clk_vdd_class *gpu_cc_lahaina_regulators[] = {

	&vdd_mx,

	&vdd_cx,

};



enum {
@@ -49,7 +51,7 @@ static const struct alpha_pll_config gpu_cc_pll0_config = { 
	.alpha = 0x6000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,
@@ -91,7 +93,7 @@ static const struct alpha_pll_config gpu_cc_pll1_config = { 
	.alpha = 0xAAA,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,
@@ -136,8 +138,8 @@ static const struct parent_map gpu_cc_parent_map_0[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gpu_cc_parent_data_0_ao[] = {

	{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },

static const struct clk_parent_data gpu_cc_parent_data_0[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .hw = &gpu_cc_pll0.clkr.hw },

	{ .hw = &gpu_cc_pll1.clkr.hw },

	{ .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
@@ -154,8 +156,8 @@ static const struct parent_map gpu_cc_parent_map_1[] = { 
	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gpu_cc_parent_data_1_ao[] = {

	{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },

static const struct clk_parent_data gpu_cc_parent_data_1[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .hw = &gpu_cc_pll1.clkr.hw },

	{ .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },

	{ .fw_name = "gcc_gpu_gpll0_div_clk_src", .name =
@@ -180,11 +182,18 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { 
	.flags = HW_CLK_CTRL_MODE,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_gmu_clk_src",

		.parent_data = gpu_cc_parent_data_0_ao,

		.parent_data = gpu_cc_parent_data_0,

		.num_parents = 6,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},

	.clkr.vdd_data = {

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 200000000,

			[VDD_LOW] = 500000000},

	},

};



static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
@@ -204,11 +213,19 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = { 
	.flags = HW_CLK_CTRL_MODE,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_hub_clk_src",

		.parent_data = gpu_cc_parent_data_1_ao,

		.parent_data = gpu_cc_parent_data_1,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},

	.clkr.vdd_data = {

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 150000000,

			[VDD_LOW] = 240000000,

			[VDD_NOMINAL] = 300000000},

	},

};



static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
@@ -261,7 +278,7 @@ static struct clk_branch gpu_cc_ahb_clk = { 


static struct clk_branch gpu_cc_cb_clk = {

	.halt_reg = 0x1170,

	.halt_check = BRANCH_HALT_SKIP,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1170,

		.enable_mask = BIT(0),
@@ -305,7 +322,7 @@ static struct clk_branch gpu_cc_cx_apb_clk = { 


static struct clk_branch gpu_cc_cx_gmu_clk = {

	.halt_reg = 0x1098,

	.halt_check = BRANCH_HALT_SKIP,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x1098,

		.enable_mask = BIT(0),

drivers/clk/qcom/videocc-lahaina.c

+10 −4
Original line number Diff line number Diff line
@@ -50,7 +50,10 @@ static const struct alpha_pll_config video_pll0_config = { 
	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -89,7 +92,10 @@ static const struct alpha_pll_config video_pll1_config = { 
	.alpha = 0xC000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,

	.config_ctl_hi1_val = 0x029A699C,

	.config_ctl_hi1_val = 0x2A9A699C,

	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000000,

	.test_ctl_hi1_val = 0x01800000,

	.user_ctl_val = 0x00000000,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x00000000,
@@ -357,7 +363,7 @@ static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { 


static struct clk_branch video_cc_ahb_clk = {

	.halt_reg = 0xe58,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0xe58,

	.hwcg_bit = 1,

	.clkr = {
@@ -455,7 +461,7 @@ static struct clk_branch video_cc_mvs1_div2_clk = { 


static struct clk_branch video_cc_mvs1c_clk = {

	.halt_reg = 0xcd4,

	.halt_check = BRANCH_HALT_VOTED,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0xcd4,

		.enable_mask = BIT(0),