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Commit 1f63a0af authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add support for CPUFREQ HW for HOLI"

parents cf7a69b1 4c24c932

qcom/holi.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -57,6 +58,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -74,6 +76,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_2>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -91,6 +94,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_3>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -108,6 +112,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_4>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -125,6 +130,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_5>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -142,6 +148,7 @@ 
			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <324>;

			next-level-cache = <&L2_6>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -159,6 +166,7 @@ 
			capacity-dmips-mhz = <1740>;

			dynamic-power-coefficient = <324>;

			next-level-cache = <&L2_7>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -623,6 +631,18 @@ 
		#reset-cells = <1>;

	};



	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw-epss";

		reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;

		reg-names = "freq-domain0", "freq-domain1";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		qcom,lut-row-size = <4>;

		qcom,max-lut-entries = <12>;

		qcom,skip-enable-check;

		#freq-domain-cells = <2>;

	};



	tcsr_mutex_block: syscon@340000 {

		compatible = "syscon";

		reg = <0x340000 0x20000>;