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Commit 1f41dc5e authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'ena-next' 



Arthur Kiyanovski says:

====================
Improving performance and reducing latencies, by using latest capabilities exposed in ENA device

This patchset introduces the following:
1. A new placement policy of Tx headers and descriptors, which takes
advantage of an option to place headers + descriptors in device memory
space. This is sometimes referred to as LLQ - low latency queue.
The patch set defines the admin capability, maps the device memory as
write-combined, and adds a mode in transmit datapath to do header +
descriptor placement on the device.
2. Support for RX checksum offloading
3. Miscelaneous small improvements and code cleanups

Note: V1 of this patchset was created as if patches e2a322a0 248ab773
from net were applied to net-next before applying the patchset. This V2
version does not assume this, and should be applyed directly on net-next
without the aformentioned patches.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 7b68b836 be26667c

drivers/net/ethernet/amazon/ena/ena_admin_defs.h

+235 −190
Original line number Diff line number Diff line
@@ -32,71 +32,49 @@ 
#ifndef _ENA_ADMIN_H_

#define _ENA_ADMIN_H_





enum ena_admin_aq_opcode {

	ENA_ADMIN_CREATE_SQ                         = 1,



	ENA_ADMIN_DESTROY_SQ                        = 2,



	ENA_ADMIN_CREATE_CQ                         = 3,



	ENA_ADMIN_DESTROY_CQ                        = 4,



	ENA_ADMIN_GET_FEATURE                       = 8,



	ENA_ADMIN_SET_FEATURE                       = 9,



	ENA_ADMIN_GET_STATS                         = 11,

};



enum ena_admin_aq_completion_status {

	ENA_ADMIN_SUCCESS                           = 0,



	ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,



	ENA_ADMIN_BAD_OPCODE                        = 2,



	ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,



	ENA_ADMIN_MALFORMED_REQUEST                 = 4,



	/* Additional status is provided in ACQ entry extended_status */

	ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,



	ENA_ADMIN_UNKNOWN_ERROR                     = 6,

	ENA_ADMIN_RESOURCE_BUSY                     = 7,

};



enum ena_admin_aq_feature_id {

	ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,



	ENA_ADMIN_MAX_QUEUES_NUM                    = 2,



	ENA_ADMIN_HW_HINTS                          = 3,



	ENA_ADMIN_LLQ                               = 4,

	ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,



	ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,



	ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG      = 12,



	ENA_ADMIN_MTU                               = 14,



	ENA_ADMIN_RSS_HASH_INPUT                    = 18,



	ENA_ADMIN_INTERRUPT_MODERATION              = 20,



	ENA_ADMIN_AENQ_CONFIG                       = 26,



	ENA_ADMIN_LINK_CONFIG                       = 27,



	ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,



	ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,

};



enum ena_admin_placement_policy_type {

	/* descriptors and headers are in host memory */

	ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,



	/* descriptors and headers are in device memory (a.k.a Low Latency

	 * Queue)

	 */
@@ -105,38 +83,26 @@ enum ena_admin_placement_policy_type { 


enum ena_admin_link_types {

	ENA_ADMIN_LINK_SPEED_1G                     = 0x1,



	ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,



	ENA_ADMIN_LINK_SPEED_5G                     = 0x4,



	ENA_ADMIN_LINK_SPEED_10G                    = 0x8,



	ENA_ADMIN_LINK_SPEED_25G                    = 0x10,



	ENA_ADMIN_LINK_SPEED_40G                    = 0x20,



	ENA_ADMIN_LINK_SPEED_50G                    = 0x40,



	ENA_ADMIN_LINK_SPEED_100G                   = 0x80,



	ENA_ADMIN_LINK_SPEED_200G                   = 0x100,



	ENA_ADMIN_LINK_SPEED_400G                   = 0x200,

};



enum ena_admin_completion_policy_type {

	/* completion queue entry for each sq descriptor */

	ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,



	/* completion queue entry upon request in sq descriptor */

	ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,



	/* current queue head pointer is updated in OS memory upon sq

	 * descriptor request

	 */

	ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,



	/* current queue head pointer is updated in OS memory for each sq

	 * descriptor

	 */
@@ -149,13 +115,11 @@ enum ena_admin_completion_policy_type { 
 */

enum ena_admin_get_stats_type {

	ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,



	ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,

};



enum ena_admin_get_stats_scope {

	ENA_ADMIN_SPECIFIC_QUEUE                    = 0,



	ENA_ADMIN_ETH_TRAFFIC                       = 1,

};
@@ -227,7 +191,9 @@ struct ena_admin_acq_common_desc { 


	u16 extended_status;



	/* serves as a hint what AQ entries can be revoked */

	/* indicates to the driver which AQ entry has been consumed by the

	 *    device and could be reused

	 */

	u16 sq_head_indx;

};
@@ -297,7 +263,6 @@ struct ena_admin_aq_create_sq_cmd { 


enum ena_admin_sq_direction {

	ENA_ADMIN_SQ_DIRECTION_TX                   = 1,



	ENA_ADMIN_SQ_DIRECTION_RX                   = 2,

};
@@ -483,8 +448,85 @@ struct ena_admin_device_attr_feature_desc { 
	u32 max_mtu;

};



enum ena_admin_llq_header_location {

	/* header is in descriptor list */

	ENA_ADMIN_INLINE_HEADER                     = 1,

	/* header in a separate ring, implies 16B descriptor list entry */

	ENA_ADMIN_HEADER_RING                       = 2,

};



enum ena_admin_llq_ring_entry_size {

	ENA_ADMIN_LIST_ENTRY_SIZE_128B              = 1,

	ENA_ADMIN_LIST_ENTRY_SIZE_192B              = 2,

	ENA_ADMIN_LIST_ENTRY_SIZE_256B              = 4,

};



enum ena_admin_llq_num_descs_before_header {

	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0     = 0,

	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1     = 1,

	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2     = 2,

	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4     = 4,

	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8     = 8,

};



/* packet descriptor list entry always starts with one or more descriptors,

 * followed by a header. The rest of the descriptors are located in the

 * beginning of the subsequent entry. Stride refers to how the rest of the

 * descriptors are placed. This field is relevant only for inline header

 * mode

 */

enum ena_admin_llq_stride_ctrl {

	ENA_ADMIN_SINGLE_DESC_PER_ENTRY             = 1,

	ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY          = 2,

};



struct ena_admin_feature_llq_desc {

	u32 max_llq_num;



	u32 max_llq_depth;



	/*  specify the header locations the device supports. bitfield of

	 *    enum ena_admin_llq_header_location.

	 */

	u16 header_location_ctrl_supported;



	/* the header location the driver selected to use. */

	u16 header_location_ctrl_enabled;



	/* if inline header is specified - this is the size of descriptor

	 *    list entry. If header in a separate ring is specified - this is

	 *    the size of header ring entry. bitfield of enum

	 *    ena_admin_llq_ring_entry_size. specify the entry sizes the device

	 *    supports

	 */

	u16 entry_size_ctrl_supported;



	/* the entry size the driver selected to use. */

	u16 entry_size_ctrl_enabled;



	/* valid only if inline header is specified. First entry associated

	 *    with the packet includes descriptors and header. Rest of the

	 *    entries occupied by descriptors. This parameter defines the max

	 *    number of descriptors precedding the header in the first entry.

	 *    The field is bitfield of enum

	 *    ena_admin_llq_num_descs_before_header and specify the values the

	 *    device supports

	 */

	u16 desc_num_before_header_supported;



	/* the desire field the driver selected to use */

	u16 desc_num_before_header_enabled;



	/* valid only if inline was chosen. bitfield of enum

	 *    ena_admin_llq_stride_ctrl

	 */

	u16 descriptors_stride_ctrl_supported;



	/* the stride control the driver selected to use */

	u16 descriptors_stride_ctrl_enabled;

};



struct ena_admin_queue_feature_desc {

	/* including LLQs */

	u32 max_sq_num;



	u32 max_sq_depth;
@@ -493,9 +535,9 @@ struct ena_admin_queue_feature_desc { 


	u32 max_cq_depth;



	u32 max_llq_num;

	u32 max_legacy_llq_num;



	u32 max_llq_depth;

	u32 max_legacy_llq_depth;



	u32 max_header_size;
@@ -584,7 +626,6 @@ struct ena_admin_feature_offload_desc { 


enum ena_admin_hash_functions {

	ENA_ADMIN_TOEPLITZ                          = 1,



	ENA_ADMIN_CRC32                             = 2,

};
@@ -612,27 +653,17 @@ struct ena_admin_feature_rss_flow_hash_function { 
/* RSS flow hash protocols */

enum ena_admin_flow_hash_proto {

	ENA_ADMIN_RSS_TCP4                          = 0,



	ENA_ADMIN_RSS_UDP4                          = 1,



	ENA_ADMIN_RSS_TCP6                          = 2,



	ENA_ADMIN_RSS_UDP6                          = 3,



	ENA_ADMIN_RSS_IP4                           = 4,



	ENA_ADMIN_RSS_IP6                           = 5,



	ENA_ADMIN_RSS_IP4_FRAG                      = 6,



	ENA_ADMIN_RSS_NOT_IP                        = 7,



	/* TCPv6 with extension header */

	ENA_ADMIN_RSS_TCP6_EX                       = 8,



	/* IPv6 with extension header */

	ENA_ADMIN_RSS_IP6_EX                        = 9,



	ENA_ADMIN_RSS_PROTO_NUM                     = 16,

};
@@ -640,19 +671,14 @@ enum ena_admin_flow_hash_proto { 
enum ena_admin_flow_hash_fields {

	/* Ethernet Dest Addr */

	ENA_ADMIN_RSS_L2_DA                         = BIT(0),



	/* Ethernet Src Addr */

	ENA_ADMIN_RSS_L2_SA                         = BIT(1),



	/* ipv4/6 Dest Addr */

	ENA_ADMIN_RSS_L3_DA                         = BIT(2),



	/* ipv4/6 Src Addr */

	ENA_ADMIN_RSS_L3_SA                         = BIT(3),



	/* tcp/udp Dest Port */

	ENA_ADMIN_RSS_L4_DP                         = BIT(4),



	/* tcp/udp Src Port */

	ENA_ADMIN_RSS_L4_SP                         = BIT(5),

};
@@ -694,14 +720,12 @@ struct ena_admin_feature_rss_flow_hash_input { 


enum ena_admin_os_type {

	ENA_ADMIN_OS_LINUX                          = 1,



	ENA_ADMIN_OS_WIN                            = 2,



	ENA_ADMIN_OS_DPDK                           = 3,



	ENA_ADMIN_OS_FREEBSD                        = 4,



	ENA_ADMIN_OS_IPXE                           = 5,

	ENA_ADMIN_OS_ESXI			    = 6,

	ENA_ADMIN_OS_GROUPS_NUM			    = 6,

};



struct ena_admin_host_info {
@@ -723,11 +747,27 @@ struct ena_admin_host_info { 
	/* 7:0 : major

	 * 15:8 : minor

	 * 23:16 : sub_minor

	 * 31:24 : module_type

	 */

	u32 driver_version;



	/* features bitmap */

	u32 supported_network_features[4];

	u32 supported_network_features[2];



	/* ENA spec version of driver */

	u16 ena_spec_version;



	/* ENA device's Bus, Device and Function

	 * 2:0 : function

	 * 7:3 : device

	 * 15:8 : bus

	 */

	u16 bdf;



	/* Number of CPUs */

	u16 num_cpus;



	u16 reserved;

};



struct ena_admin_rss_ind_table_entry {
@@ -800,6 +840,8 @@ struct ena_admin_get_feat_resp { 


		struct ena_admin_device_attr_feature_desc dev_attr;



		struct ena_admin_feature_llq_desc llq;



		struct ena_admin_queue_feature_desc max_queue;



		struct ena_admin_feature_aenq_desc aenq;
@@ -847,6 +889,9 @@ struct ena_admin_set_feat_cmd { 


		/* rss indirection table */

		struct ena_admin_feature_rss_ind_table ind_table;



		/* LLQ configuration */

		struct ena_admin_feature_llq_desc llq;

	} u;

};
@@ -876,23 +921,16 @@ struct ena_admin_aenq_common_desc { 
/* asynchronous event notification groups */

enum ena_admin_aenq_group {

	ENA_ADMIN_LINK_CHANGE                       = 0,



	ENA_ADMIN_FATAL_ERROR                       = 1,



	ENA_ADMIN_WARNING                           = 2,



	ENA_ADMIN_NOTIFICATION                      = 3,



	ENA_ADMIN_KEEP_ALIVE                        = 4,



	ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,

};



enum ena_admin_aenq_notification_syndrom {

	ENA_ADMIN_SUSPEND                           = 0,



	ENA_ADMIN_RESUME                            = 1,



	ENA_ADMIN_UPDATE_HINTS                      = 2,

};
@@ -1008,6 +1046,13 @@ struct ena_admin_ena_mmio_req_read_less_resp { 
#define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)

#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT                 16

#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)

#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT               24

#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)

#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)

#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT                    3

#define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)

#define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8

#define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)



/* aenq_common_desc */

#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)