Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1ef28870 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Octeon: Remove vestiges of CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB 



The config option CAVIUM_RESERVE32_USE_WIRED_TLB is not supported.
Remove the dead code controlled by it.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1028/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1874a088

arch/mips/cavium-octeon/setup.c

+1 −66
Original line number Diff line number Diff line
@@ -186,54 +186,6 @@ void octeon_check_cpu_bist(void) 
	write_octeon_c0_dcacheerr(0);

}



#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB

/**

 * Called on every core to setup the wired tlb entry needed

 * if CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB is set.

 *

 */

static void octeon_hal_setup_per_cpu_reserved32(void *unused)

{

	/*

	 * The config has selected to wire the reserve32 memory for all

	 * userspace applications. We need to put a wired TLB entry in for each

	 * 512MB of reserve32 memory. We only handle double 256MB pages here,

	 * so reserve32 must be multiple of 512MB.

	 */

	uint32_t size = CONFIG_CAVIUM_RESERVE32;

	uint32_t entrylo0 =

		0x7 | ((octeon_reserve32_memory & ((1ul << 40) - 1)) >> 6);

	uint32_t entrylo1 = entrylo0 + (256 << 14);

	uint32_t entryhi = (0x80000000UL - (CONFIG_CAVIUM_RESERVE32 << 20));

	while (size >= 512) {

#if 0

		pr_info("CPU%d: Adding double wired TLB entry for 0x%lx\n",

			smp_processor_id(), entryhi);

#endif

		add_wired_entry(entrylo0, entrylo1, entryhi, PM_256M);

		entrylo0 += 512 << 14;

		entrylo1 += 512 << 14;

		entryhi += 512 << 20;

		size -= 512;

	}

}

#endif /* CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB */



/**

 * Called to release the named block which was used to made sure

 * that nobody used the memory for something else during

 * init. Now we'll free it so userspace apps can use this

 * memory region with bootmem_alloc.

 *

 * This function is called only once from prom_free_prom_memory().

 */

void octeon_hal_setup_reserved32(void)

{

#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB

	on_each_cpu(octeon_hal_setup_per_cpu_reserved32, NULL, 0, 1);

#endif

}



/**

 * Reboot Octeon

 *
@@ -502,25 +454,13 @@ void __init prom_init(void) 
	 * memory when it is getting memory from the

	 * bootloader. Later, after the memory allocations are

	 * complete, the reserve32 will be freed.

	 */

#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB

	if (CONFIG_CAVIUM_RESERVE32 & 0x1ff)

		pr_err("CAVIUM_RESERVE32 isn't a multiple of 512MB. "

		       "This is required if CAVIUM_RESERVE32_USE_WIRED_TLB "

		       "is set\n");

	else

		addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,

							0, 0, 512 << 20,

							"CAVIUM_RESERVE32", 0);

#else

	/*

	 *

	 * Allocate memory for RESERVED32 aligned on 2MB boundary. This

	 * is in case we later use hugetlb entries with it.

	 */

	addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,

						0, 0, 2 << 20,

						"CAVIUM_RESERVE32", 0);

#endif

	if (addr < 0)

		pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");

	else
@@ -817,9 +757,4 @@ void prom_free_prom_memory(void) 
		panic("Unable to request_irq(OCTEON_IRQ_RML)\n");

	}

#endif



	/* This call is here so that it is performed after any TLB

	   initializations. It needs to be after these in case the

	   CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */

	octeon_hal_setup_reserved32();

}