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Commit 1ea4fe84 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/boot' into x86/mm, to unify branches 



Both x86/mm and x86/boot contain 5-level paging related patches,
unify them to have a single tree to work against.

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents ef61f8a3 4440977b

arch/x86/boot/compressed/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ vmlinux-objs-y := $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \ 
vmlinux-objs-$(CONFIG_EARLY_PRINTK) += $(obj)/early_serial_console.o

vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr.o

ifdef CONFIG_X86_64

	vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/pagetable.o

	vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr_64.o

	vmlinux-objs-y += $(obj)/mem_encrypt.o

	vmlinux-objs-y += $(obj)/pgtable_64.o

endif

arch/x86/boot/compressed/head_64.S

+19 −22
Original line number Diff line number Diff line
@@ -304,20 +304,6 @@ ENTRY(startup_64) 
	/* Set up the stack */

	leaq	boot_stack_end(%rbx), %rsp



#ifdef CONFIG_X86_5LEVEL

	/*

	 * Check if we need to enable 5-level paging.

	 * RSI holds real mode data and need to be preserved across

	 * a function call.

	 */

	pushq	%rsi

	call	l5_paging_required

	popq	%rsi



	/* If l5_paging_required() returned zero, we're done here. */

	cmpq	$0, %rax

	je	lvl5



	/*

	 * At this point we are in long mode with 4-level paging enabled,

	 * but we want to enable 5-level paging.
@@ -325,12 +311,28 @@ ENTRY(startup_64) 
	 * The problem is that we cannot do it directly. Setting LA57 in

	 * long mode would trigger #GP. So we need to switch off long mode

	 * first.

	 */



	/*

	 * paging_prepare() sets up the trampoline and checks if we need to

	 * enable 5-level paging.

	 *

	 * NOTE: This is not going to work if bootloader put us above 4G

	 * limit.

	 * Address of the trampoline is returned in RAX.

	 * Non zero RDX on return means we need to enable 5-level paging.

	 *

	 * The first step is go into compatibility mode.

	 * RSI holds real mode data and needs to be preserved across

	 * this function call.

	 */

	pushq	%rsi

	call	paging_prepare

	popq	%rsi



	/* Save the trampoline address in RCX */

	movq	%rax, %rcx



	/* Check if we need to enable 5-level paging */

	cmpq	$0, %rdx

	jz	lvl5



	/* Clear additional page table */

	leaq	lvl5_pgtable(%rbx), %rdi
@@ -352,7 +354,6 @@ ENTRY(startup_64) 
	pushq	%rax

	lretq

lvl5:

#endif



	/* Zero EFLAGS */

	pushq	$0
@@ -490,7 +491,6 @@ relocated: 
	jmp	*%rax



	.code32

#ifdef CONFIG_X86_5LEVEL

compatible_mode:

	/* Setup data and stack segments */

	movl	$__KERNEL_DS, %eax
@@ -526,7 +526,6 @@ compatible_mode: 
	movl	%eax, %cr0



	lret

#endif



no_longmode:

	/* This isn't an x86-64 CPU so hang */
@@ -585,7 +584,5 @@ boot_stack_end: 
	.balign 4096

pgtable:

	.fill BOOT_PGT_SIZE, 1, 0

#ifdef CONFIG_X86_5LEVEL

lvl5_pgtable:

	.fill PAGE_SIZE, 1, 0
 
#endif

arch/x86/boot/compressed/pgtable_64.c

+12 −13
Original line number Diff line number Diff line
@@ -9,20 +9,19 @@ 
 */

unsigned long __force_order;



int l5_paging_required(void)

{

	/* Check if leaf 7 is supported. */



	if (native_cpuid_eax(0) < 7)

		return 0;

struct paging_config {

	unsigned long trampoline_start;

	unsigned long l5_required;

};



	/* Check if la57 is supported. */

	if (!(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))

		return 0;

struct paging_config paging_prepare(void)

{

	struct paging_config paging_config = {};



	/* Check if 5-level paging has already been enabled. */

	if (native_read_cr4() & X86_CR4_LA57)

		return 0;

	/* Check if LA57 is desired and supported */

	if (IS_ENABLED(CONFIG_X86_5LEVEL) && native_cpuid_eax(0) >= 7 &&

			(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))

		paging_config.l5_required = 1;



	return 1;

	return paging_config;

}