Loading qcom/holi.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -323,6 +323,25 @@ interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; }; spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, <0x1e00000 0x2000000>, <0x3e00000 0x100000>, <0x3f00000 0xa0000>, <0x1c0a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; }; arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, Loading Loading
qcom/holi.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -323,6 +323,25 @@ interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; }; spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, <0x1e00000 0x2000000>, <0x3e00000 0x100000>, <0x3f00000 0xa0000>, <0x1c0a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; }; arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, Loading