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Commit 1cf45b8f authored by Florian Fainelli's avatar Florian Fainelli Committed by Will Deacon
Browse files

arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core 



The Broadcom Brahma-B53 core is susceptible to the issue described by
ARM64_ERRATUM_843419 so this commit enables the workaround to be applied
when executing on that core.

Since there are now multiple entries to match, we must convert the
existing ARM64_ERRATUM_843419 into an erratum list and use
cpucap_multi_entry_cap_matches to match our entries.

Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent e059770c

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -93,6 +93,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_845719        |

+----------------+-----------------+-----------------+-----------------------------+

| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_843419        |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Cavium         | ThunderX ITS    | #22375,24313    | CAVIUM_ERRATUM_22375        |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/kernel/cpu_errata.c

+20 −3
Original line number Diff line number Diff line
@@ -755,6 +755,23 @@ static const struct midr_range erratum_845719_list[] = { 
};

#endif



#ifdef CONFIG_ARM64_ERRATUM_843419

static const struct arm64_cpu_capabilities erratum_843419_list[] = {

	{

		/* Cortex-A53 r0p[01234] */

		.matches = is_affected_midr_range,

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),

		MIDR_FIXED(0x4, BIT(8)),

	},

	{

		/* Brahma-B53 r0p[0] */

		.matches = is_affected_midr_range,

		ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),

	},

	{},

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -786,11 +803,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_ARM64_ERRATUM_843419

	{

	/* Cortex-A53 r0p[01234] */

		.desc = "ARM erratum 843419",

		.capability = ARM64_WORKAROUND_843419,

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),

		MIDR_FIXED(0x4, BIT(8)),

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = cpucap_multi_entry_cap_matches,

		.match_list = erratum_843419_list,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_845719