Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1cc54078 authored by Tony Lindgren's avatar Tony Lindgren Committed by Stephen Boyd
Browse files

clk: ti: clkctrl: Fix clkdm_clk handling 



We need to always call clkdm_clk_enable() and clkdm_clk_disable() even
the clkctrl clock(s) enabled for the domain do not have any gate register
bits. Otherwise clockdomains may never get enabled except when devices get
probed with the legacy "ti,hwmods" devicetree property.

Fixes: 88a17252 ("clk: ti: add support for clkctrl clocks")
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b3fddd5b

drivers/clk/ti/clkctrl.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -137,9 +137,6 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) 
	int ret;

	int ret;

	union omap4_timeout timeout = { 0 };

	union omap4_timeout timeout = { 0 };





	if (!clk->enable_bit)

		return 0;



	if (clk->clkdm) {

	if (clk->clkdm) {

		ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);

		ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);

		if (ret) {

		if (ret) {
@@ -151,6 +148,9 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) 
		}

		}

	}

	}





	if (!clk->enable_bit)

		return 0;



	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);

	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);





	val &= ~OMAP4_MODULEMODE_MASK;

	val &= ~OMAP4_MODULEMODE_MASK;
@@ -179,7 +179,7 @@ static void _omap4_clkctrl_clk_disable(struct clk_hw *hw) 
	union omap4_timeout timeout = { 0 };

	union omap4_timeout timeout = { 0 };





	if (!clk->enable_bit)

	if (!clk->enable_bit)

		return;

		goto exit;





	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);

	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);