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Commit 1c70fbac authored by Pankaj Gupta's avatar Pankaj Gupta Committed by Hareesh Gundu
Browse files

ARM: dts: msm: Add GPU properties for Holi 

Add required GPU properties to Holi to enable
graphics driver functionality.

Change-Id: I8b40055679159e989ec1f588eb24a126f5ba8fb2
parent d428ea15

qcom/holi-gpu.dtsi

0 → 100644
+194 −0
Original line number Diff line number Diff line 
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))

&soc {

	pil_gpu: qcom,kgsl-hyp {

		compatible = "qcom,pil-tz-generic";

		qcom,pas-id = <13>;

		qcom,firmware-name = "a615_zap";

		memory-region = <&pil_gpu_micro_code_mem>;

	};



msm_gpu: qcom,kgsl-3d0@5900000 {

		compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-a619-holi";

		status = "ok";

		reg = <0x5900000 0x40000>,

		    <0x5961000 0x800>,

		    <0x0596A000 0x30000>,

		    <0x599E000 0x1000>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "gmu_wrapper", "cx_misc";

		interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_3d0_irq";



		clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,

			<&gpucc GPU_CC_CXO_CLK>,

			<&gcc GCC_BIMC_GPU_AXI_CLK>,

			<&gpucc GPU_CC_AHB_CLK>,

			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,

			<&gpucc GPU_CC_CX_GMU_CLK>;



		clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",

				"iface_clk", "mem_iface_clk", "gmu_clk";



		vddcx-supply = <&gpu_cx_gdsc>;

		vdd-supply = <&gpu_gx_gdsc>;

		qcom,chipid = <0x06010900>;



		qcom,initial-pwrlevel = <4>;

		qcom,gpu-quirk-secvid-set-once;

		qcom,min-access-length = <32>;

		qcom,ubwc-mode = <2>;



		interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI>;

		interconnect-names = "gpu_icc_path";



		qcom,bus-table-ddr7 =

			<MHZ_TO_KBPS(0, 4)>,    /* index=0  */

			<MHZ_TO_KBPS(451, 4)>,  /* index=1 (LOW SVS) */

			<MHZ_TO_KBPS(547, 4)>,  /* index=2(LOW SVS) */

			<MHZ_TO_KBPS(681, 4)>,  /* index=3 (SVS) */

			<MHZ_TO_KBPS(768, 4)>,  /* index=4 (SVS) */

			<MHZ_TO_KBPS(1017, 4)>, /* index=5 (SVS) */

			<MHZ_TO_KBPS(1353, 4)>, /* index=6 (NOM) */

			<MHZ_TO_KBPS(1555, 4)>, /* index=7 (NOM) */

			<MHZ_TO_KBPS(1804, 4)>, /* index=8 (TURBO) */

			<MHZ_TO_KBPS(2092, 4)>; /* index=9 (TURBO_L1) */



		qcom,gpu-mempools {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

				qcom,mempool-allocate;

			};

			/* 8K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size = <8192>;

				qcom,mempool-allocate;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@2 {

				reg = <2>;

				qcom,mempool-page-size = <65536>;

				qcom,mempool-reserved = <256>;

			};

			/* 1M Page Pool configuration */

			qcom,gpu-mempool@3 {

				reg = <3>;

				qcom,mempool-page-size = <1048576>;

				qcom,mempool-reserved = <32>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,gpu-pwrlevels";



			/* TURBO_L1 */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <875000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;



				qcom,bus-freq-ddr7 = <9>;

				qcom,bus-min-ddr7 = <8>;

				qcom,bus-max-ddr7 = <9>;

			};



			/* TURBO */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <800000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <7>;

				qcom,bus-max-ddr7 = <9>;



			};



			/* NOM_L1 */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



				qcom,bus-freq-ddr7 = <7>;

				qcom,bus-min-ddr7 = <5>;

				qcom,bus-max-ddr7 = <9>;



			};



			/* NOM */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <565000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;



				qcom,bus-freq-ddr7 = <6>;

				qcom,bus-min-ddr7 = <5>;

				qcom,bus-max-ddr7 = <8>;



			};



			/* SVS_L1 */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <430000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;



				qcom,bus-freq-ddr7 = <5>;

				qcom,bus-min-ddr7 = <4>;

				qcom,bus-max-ddr7 = <7>;



			};



			/* SVS */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <355000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;



				qcom,bus-freq-ddr7 = <4>;

				qcom,bus-min-ddr7 = <2>;

				qcom,bus-max-ddr7= <5>;

			};



			/* LOW SVS */

			qcom,gpu-pwrlevel@6 {

				reg = <6>;

				qcom,gpu-freq = <253000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;



				qcom,bus-freq-ddr7 = <2>;

				qcom,bus-min-ddr7 = <1>;

				qcom,bus-max-ddr7 = <4>;

			};

		};

	 };



	kgsl_msm_iommu: qcom,kgsl-iommu@5940000 {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x5940000 0x10000>;



		vddcx-supply = <&gpu_cx_gdsc>;



		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&kgsl_smmu 0x0>;

			qcom,iommu-dma = "disabled";

		};



		gfx3d_secure: gfx3d_secure {

		      compatible = "qcom,smmu-kgsl-cb";

		      iommus = <&kgsl_smmu 0x2>;

		      qcom,iommu-dma = "disabled";

		};

	};

};

qcom/holi.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -2085,6 +2085,7 @@ 


#define PMK8350_SID	6



#include "holi-gpu.dtsi"

#include "holi-pinctrl.dtsi"

#include "pm6350.dtsi"

#include "pm7250b.dtsi"